dyslipidemia lipitor desyrel 100 mg 30 tablet phenergan syrup with codeine dosage provigil uk buy online phenergan codeine safe during pregnancy
March 23rd, 2021 ~ by admin

CPU of the Day: National Elentari x86 and What Lies Beyond – Part 2

Last week we talked about a little known, but not unheard of 486 built by National Semiconductor called the NS486 Elentari.  As interesting as a non-Intel x86 architecture is, thats not what led me down the aforementioned rabbit hole.  This is what did…

The entrance to the Rabbit hole lay in an issue of Boot Magazine.

This small blurb in Boot magazine from back in August of 1997 is all it took.  What was this mysterious N7 processor that even Boot Magazine felt the need to mention?  It is being compared to the Cyrix MediaGX, which coincidently National had agreed to merge with right about the time this issue went to press, a fact that may or may not have been known to the authors at the time.  Regardless, the deal wasn’t officially completed until 1998, so that meant this mysterious N7 had been in development for some time, and probably had reached something a bit more then a glitter in an engineers eyes….and indeed it had.

Mentions of the ‘N7’ in the press at the time start in early 1996 and continue through 1997, this indicates that the N7 was likely planned soon after the beginnings of the NS486 core.  Its very likely that the NS486 was to be a stepping stone to the bigger more powerful N7.  The N7 is described as a 133MHz ‘Pentium compatible’ processor.  The NS586 core (as it was called by National) was an enhanced NS486, with the pipeline extended to 5-stages and using Nationals new 0.35u process, just as some had originally suggested for the NS486.  This resulted in a 3.3V processor running at 133MHz.

NS586 5-Stage Pipeline – Cache could happen on Stage 3 or 4 and Memory Access was non-blocking (image (c) MPR)

The NS586 was planned to be at least 2, and most likely 3 different processors (in similar fashion to the NS486SXF and NS486SXL).  The common core to all of the designs was the 5-stage NS586.  This took the NS486 and greatly enhanced it, adding 8 of L1 cache (4K Instruction + 4K Data). The pre-fetch buffer is doubled in size to 32-bytes as well as some Out of Order execution support.  The decode and memory/cache access logic is also further optimized.  Cache accesses can be shifted between the 3rf and 4th stages as needed, allowing modifying, loading or storing of cache data in two consecutive cycles.  Unlike the K6 or PII the NS586 does not use intermediate instructions in executing x86 code, it directly executes each x86 instruction (like the NS486 before it).  The updated pipeline executes all code as fast or faster then a 486 and in some cases faster then a Pentium.  National claimed that the 133MHz core would perform as a Pentium 95, compared to say a AMD 5×86-133 being rated at a Pentium 75 level. As with the NS486 before it, it lacked an onchip FPU.

The NS586 core was not exactly small, even on the 0.35u process it took 930,000 transistors (426,000 of which is the cache).  This resulted in a die size of around 25.8mm2. (roughly the same size as the core only NS486 on 0.65u).  And it was intended to be even bigger…

Lise the NS486 before it, the NS586 was to be integrated with a variety of peripherals, and this time National was going big on the integration.   At the top was the N7-Lite, which integrated the NS586 core with a SVGA 2D graphics controller, TI TMS320C50 based DSP and Audio controller.  This in addition to a PCI bus, DMA controller USB, IrDA, and other normal peripherals of the era.  The N7-Lite does not have a traditional DRAM controller, instead using a controller geared towards a UMA (Unified Memory Architecture) to use the system RAM for the CPU and the onboard GPU. The GPU is designed to support only a TV out (NTSC PAL and SECAM outputs) as this was to be a full NetworkPC on a chip, basically what became Set-Top Boxes of the 1990’s.

NS586L and N7-Lite shared the same core but with different peripherals as well as busses (image (c) MPR)

On the low end was the NS586L, which dropped the audio, video, and PCI bus and added a standard Pentium compatible VL-Bus, ISA, and DRAM/ROM controller, this is more of a enhanced NS486 with a similar set of peripherals, and likely would be the logical successor to designs using the 486.  Speed was to be 100MHz (again to differentiate it from the N7-Lite) and estimated cost was to be $25/chip.  Pricing for the N7-Lite was not announced. It’s unknown how far these designs progressed, whether actual silicon was made or not.  Having a transistors count and die size was indication they were pretty far along, perhaps having the chips floor plan finalized and working on taping it out for masks (6 months seems reasonable for samples after tape out).

Both of these chips were scheduled (as of October of 1997) to begin sampling in the second quarter of 1998.  Its very likely that a third chip was planned, if only due to the naming of the ‘N7-Lite.’ ‘Lite’ indicates that it is something less then the full version, and the Boot blurb (as well as some other press mentions) only refers to the ‘N7.’  In all likelihood there was to be a top end version known simply as the N7.  Such a chip would likely replace the TV only GPU in the N7-Lite with something that supports standard CRTs or LCD panels, perhaps more RAM support and Ethernet and/or an EIDE hard drive controller (something that the competing Cyrix derived ST STPC included).  We may never know, as despite the efforts of the engineering team the project was inevitably canceled in favor of the newly acquired MediaGX line from Cyrix.  This line continued to be developed at National even after they sold the rest of Cyrix off to VIA (eventually selling the MediaGX division to AMD).

Sadly they didn’t

Perhaps someone who worked in the Arador group at National can offer more insight, but until then we can only speculate of what could have been another interesting processor on the x86 scene in the 1990’s.

Posted in:
Uncategorized

March 18th, 2021 ~ by admin

CPU of the Day: National Elentari x86 and What Lies Beyond – Part 1

National Semi NS486SXF-25 Rev C0 -1999

While I was casually reading an issue of ‘Boot’ Magazine from 1997 I was sent down the rabbit hole by a mention of a processor in a small blurb in a footnote of an article.  Just a few lines really is all, but about a processor I was not familiar with, an x86 one at that! So nearly a month later, I have emerged from the rabbit hole.  We will begin not with what sent me to the hole in the first place, but when and where the hole itself came from, and that is the year 1995, the place? National Semiconductor.

As mentioned in the 486 Overclocking article, the 1990’s were a boon for up and coming x86 processors.  In some ways it was similar to the processor bonanza of the 1970’s but centered on x86.  Many companies wanted to have a go at the x86 architecture market.  National Semiconductor was of course interested in making something with x86 as well.  They rightly decided that a head to head competition with Intel for mainstream PC processors wasn’t the best idea, but that embedded computing, low cost set top box (as they later would become) and ‘Network PC’s’ would be a good market.  The goal was to design a simple efficient x86 processor and integrate it with many peripherals, and sell it for $20-30 each.

Elentari Core. 16-byte Prefetch Buffer, 1K Cache ,16-bit Data Bus and support for 2 8M DRAM Pages

 

NS486SXF/L Block Diagram (SXL omits blocks in dashed lines)

The core project began in very early 1995 (or late 1994) and was known as the Elantari, Queen of the Stars in Lord of the Rings Mythology.  The Elantari (aka the ESF94001) had three priorities in its development (in order): 1) Schedule, 2) Low Cost, 3) Performance.  Time to market was essential, even at the expense of performance optimization. The core (which the Marketing dept quickly renamed to the NS486) was to be a 486 compatible core (using protected mode only) with some optimizations and was organized officially under a new unit at National Semiconductor called the Arador Unit (someone really liked LotR). Target speed was 25MHz at 5V on Nationals 0.65u process using a very simple 3-stage pipeline (Fetch/Decode, Execute, Write Back).

NS486SXL-25 No Rev Marked 1996 (courtesy xSecret)

Balancing cost and performance meant that die area should be minimized, as this effects yields and parts per wafer.  This, on a 0.65u process, allowed for a small area of cache.  National ended up, after a fair amount of analysis, going with a 1K direct mapped instruction cache (that can bus snoop) and a 16 byte prefetch buffer.  This is in great contrast to the Intel 486 which had a 8KB unified cache (and 16K on later 486s).  But for embedded use instructions have a better performance increase when cached then data.  Cache also presents some difficulties with real time computing, as its difficult to know how long an operation will take if you don’t also know whether it s from cache or the main memory.  National provided a method on the NS486 to load and lock the cache with a set of instructions that would ALWAYS operate out of cache.  This combined with assigning one DRAM page to Data, and another for stack use, made timing more predictable and consistent when needed.  As part of the development process National used IP they had licensed from another IIT, whom had earlier designed a 486 class processor. IITs IP was not used in the NS486 itself, but was used in helping debug, design and develop it and its testing environment.

NS486SXL-25 Rev A – SXL unique die – 1998

The NS486 core lacked both a FPU and MMU, and had a 16-bit data bus.  This allowed for a fairly small core size.  The core alone took up about 256,000 transistors (roughly half of what the Intel 486 integer core used) and on the initial 0.65u 3-layer process results in a core die size of 29.6mm2 including the cache. (the SXL die with limited peripherals pushed that to around 64mm2)  The short pipeline greatly restricts the speed, it never made it above 25MHz (though 33MHz was apparently achievable.

National Semiconductor by this time had become dominate in integrated peripheral chips, led by its ‘SuperIO’ chip line, and it was this integration that made the NS486 unique.  National designed two versions of the NS486, the NS486SXF with a full set of peripherals, and the smaller NS486SXL with a few less.  The integration of peripherals was one of the most challenging aspects, the core itself is relatively simple, but adding other features, often with different clock and signal domains is much harder to design and test.  This is where National’s expertise on SuperIO chips came in handy.

The other challenging aspect of a x86 design in the 1990’s was from the legal department.  Intel claimed that even a clean design of anything x86 ‘MUST’ violate at least one Intel patent.  National however had designed the NS486 from the ground up, including the microcode, AND as a backup, also possessed a license from Intel dating back to the 1970’s (it was that license that helped lead to the National/Cyrix merger).

  NS486SXF NS486SXL
Package 160PQFP 132PQFP
Cost $25 $15
486 Core
X
X
DRAM Controller
X
X
DMA Controller
X

LCD Controller
X

ISA Bus Interface
X
X
External Bus Master Controller

X
UART/IrDA
X
X
ECP Parallel Port
X

PCMCIA Controller
X

Real-Time Clock, Timers
X
X
Programmable Interrupt
X
X
Reconfigurable I/O
X
X
Programmable Chip Select
X
X
3-Wire Serial Peripheral
X
X

NS486SXL Rev A0 die – matches package markings – Still 0.65u (courtesy aberco)

Initially both the NS486SXL and SXF used the same die, with the SXL having some of the onchip features disabled. National planned on making a seperate die later for the SXL to further reduce costs.  They did this in around 1998.  Their goal was also to shrink the design to their upcoming 0.35u process but it is unknown if they successfully did this (dies from 1998 continue to be of the 0.65u variety).

Initial samples were available by early 1996, a rather quick development.  The NS486 was well supported in both hardware and software.  It supported a number of common real-time operating systems of the time, including pSOS+, QNX, VxWorks, and VRTX. It did not however support DOS, having no real mode support. In 1997 the NS486SXF was used to implement Jav Nanokernel, a Java based OS running the Java VM directly on hardware. Hardware vendors included PARVUS (NS486 based PC104 board), BCT (Dev Boards) and several others making ready made NS486 based SBCs.   In November of 1996 National released a full Web Browser based Network computer Reference design using the NS486 called the ‘Odin’  This was the first sub-$200 web browser capable computer of the time.

NS486SXL die – Peripherals take up about a third of the die (die photo from aberco)

In 1997 things got a bit more interesting.  National Semiconductor decided to merge (in all reality it was an acquisition) with Cyrix.  The NS486 continued to be made, but by 1999 National listed it as ‘not recommended for new designs’  It would also appear that some things never really got finished.  Datasheets up through at least Dec of 1997 were still ‘Preliminary’ though the silicon had been produced for sometime.  Production of the NS486 continued well into the 2000s, with chips being made at least into 2003 and probably later.

The NS486 Performance in integer tasks was pretty good. In some cases beating the Intel 486DX. THis is largely because of its optimized instruction timing, many are single cycle, much faster then other cores.

At the time of its introduction it had little competition (in the x86 realm).  Intel had the 386EX and AMD had an the 386SC (what later became the ElanSC300 line).  Both of these were 386 class parts that were slower (and in the case of the 386EX) more expensive.  Intel themselves did not have a good embedded 486 option largely due to lack of trailing edge fab capacity.  Most of their fabs had been (or were being) converted to higher end processes to make new Pentiums and P6 chips, while their older fabs were filled to the brim with Intel’s then booming chipset business.

ARM 610 Motorola 68349 Hitachi SH7032 NEC V820 MIPS LR33020 Intel i960CA AMD 386SC Intel 386EX NS486SXF
Frequency 20 MHz 25 MHz 20 MHz 25 MHz 25 MHz 25 MHz  25 MHz  25 MHz 25MHz
Dhrystone MIPS 18 9 16 18 14 30 5.4 7.1 12
FPU No No No Yes No No No No No
MMU No No No No No No Yes No No
Cache None 1K Inst None 1K Inst 4K/4K 1K Inst None None 1K Inst
Periphs. Some Some Some Some Some Some Full Set Some Full Set
Transistors 359k 550k 593k 380k 700k 600k 335k ?? 500k*
Process 1.0u 0.8u 0.8u 0.8u 0.7u 1.0u 0.7u 0.8u 0.65u
Price $20 $33 $30 $80 $67 $90 $49 $33 $25

*Estimated Core = 256k Cache = ~50k

It was suggested that if National lengthened the pipeline of the NS486 to the then standard 5-stages, and moved it to their new 0.35u process that it could ‘easily’ hit 133MHz at 3.3V.  But what embedded designer would want to have to deal with that fast of a processor?  It would seem that the NS486 team had ideas beyond just the purely embedded market, as something more then the NS486 was their ultimate goal, and exactly what led me down this Rabbit hole……

In Part 2 we’ll look at what National developed from the NS486, and if it wasn’t for the MediaGX they acquired, very likely would have made it to market.

Posted in:
CPU of the Day

March 10th, 2021 ~ by admin

The Story of the Soviet 8080 Processor – The 580

Before beginning the history of the Soviet 580 series microprocessor, we need to say a little bit about the level of Soviet computing technology before the advent of integrated microprocessors. This is really a topic for a separate article, so just two facts.

This article is largely from guest author Vladimir Yakovlev, translated from Russian, and edited/expanded by me.  It is part of a series on Soviet microprocessors that started with the Soviet T34 Z80 article. 

In 1950 the “Small Electronic Computing Machine” (SECM) was made in the USSR. It should be noted that in the USSR this computer was launched at a time when there was only a few computers in Europe, the English EDSAK, launched just a year earlier and Zuse’s Z4 in Zurich in ~1947. But the processor of SECM was much more powerful by parallelizing the computational process.

In the creation of the SECM, all fundamental principles of computer creation were used, such as the presence of input and output devices, the encoding and storage of the program in memory, the automatic execution of the computation based on the stored program, etc. Most importantly, it was a computer based on binary logic used and currently used in computational engineering (the American ENIAC used a decimal system (!!!)).

In 1975, during the historic Soyuz-Apollo space mission, the control was carried out by the complex, which included the BECM-6 (Big Electronic Computing Machine), a direct descendant of SECM. This system allowed for one minute of flight computation time, while on the American side of the flight it took 30 minutes of computation.

BECM-6 (Science Museum, London)

The real tragedy was the decision to produce IBM-360 clones in the USSR, that is, the transition to copying American architecture. I mean, obviously, whoever’s copying doesn’t have a chance to outrun (THe the USSR regularly added enhancements to Western designs). Copying has only one meaning – as a stage of learning. When you don’t have your own technology. Today, China is demonstrating the effectiveness of this approach. But the logical end of such an approach is still a shift to proprietary developments.

From that moment on, the Soviet Union was catching up.

At the end of 1962, by the decision of the Government of the USSR, the Kiev Design Bureau was established in Kiev, later the Kiev Institute of Microdevices (KNIIMP), with an experienced plant. It was KNIIMP that was chosen to copy Intel’s products. The first task was to create a copy of the i8080 and was started in August 1976, just 2 years after Intel introduced the 8080 to the Western World.

In 1977-1978, the first prototype chips were completed. The first basic set of the series contained three chips, K580IK80 (8080 CPU), K580IK51 (8251 USART) and K580IK55 (8255 PIO Controller).

They were produced in 48-lead metal-ceramic planar package. Contrary to popular belief, it is not a layer-by-layer copy of the Intel 8080 (some blocks are similar, but the layout and location of the bonding pads are significantly different). On November 6, 1980, the New York Times published an article “Soviet Gaining in Computers”.  in which the author of article also reached this conclusion.  These ran at 2MHz (500,000 ops/ec) and were made on a 6 micron NMOS process.

In 1981-1982 the package were replaced with the standard (Soviet pin spacing) DIP. Both versions for the domestic economy in plastic cases and for special applications in metal ceramics were released.

580VM80 – 1988 – Military spec

Around 1983, the names were changed from IK80 to VM80, IK55 and IK51 to VV55 and VV51 respectively. The additional letter “A” denotes an upgraded version of the processor from the extended base set of the series. In this variant, the speed was increased to 2.5MHz 625,000 op/s, the area of the die was reduced by 20%, (resulting from a process shrink to 5 microns) and the periphery of the crystal was redesigned.

KR580IK80A – 2.5MHz – 1982 – “KWAZAR” (KIEV, UKRAINE)

The 580 series was produced by many of the Soviet IC design houses, for many years.  Including, Kvazar, Electronpribor, Rodon, Kvator and Dnepr.

 

KR580IK80A “ELECTRONPRIBOR” (FRYAZINO, RUSSIA)
( “O” – pre-production sample)

“KVANTOR” (ZBARAGH, UKRAINE)

“RODON” (IVANO-FRANKIVSK, UKRAINE)
Top package is a early (1983) ‘Chocolate’ Brown PDIP

Late Production (1991) KR580VM80A – “DNEPR” (KHERSON, UKRAINE)

Chips manufactured for export were marked with the inscription Сделано в СССР and didn’t have the logo of the manufacturer.  The ‘manufacturer’ was the USSR, as that was more important then which state enterprise it came from, as a matter of national pride.

Export version (for Export to other Soviet Aligned countries)

In a sense, reproduction of microcircuit analogues is akin to a very high quality translation of foreign literature into native language. It is necessary not only to completely transfer the purpose of the product itself, but also to make it technologically compatible for the domestic producer. This is a very difficult task.

While the 8080 and 8086 microprocessors were at issue, the KNIIMP was successfully performing its task. But once Intel developed and started the 80286 and then the 80386, the Soviet Union was unable to produce similar microprocessors.

It can be argued that Intel Vice President Robert Noyce’s suggestion has been fully realized – the Soviet Union had fallen behind the United States in the development and production of modern microprocessor circuits forever.  Even to this day Russia continues to make variants of Western processors, from the MCS-96 series, to Microchip PIC17’s.  It should be noted that they did make a myriad of somewhat custom microcontrollers for specific tasks, that did not have direct Western Analogs (though sometimes they claimed these devices to be analogs of chips that they were not, in order to meet the direction of ‘copy the West’)

 

Posted in:
CPU of the Day

February 25th, 2021 ~ by admin

The 486 CPU Era – The Birth of Overclocking. – Part 2

In Part 1 of The 486 CPU Era – The Birth of Overclocking, we covered some of the basics of the 486 era and where it came from, as well as the various brands/types of 486s of the era (many of which we will test and attempt to overclock.  In Part 2 we will discuss the hardware selection and rational, testing environment and benchmarks! (and a healthy dose of Overclocking with some perhaps surprising results)

Choosing a Motherboard

Socket 5, GIGABYTE GA586AM, UM8891BF / UM8892BF chipset – Good but not good enough

Choosing a motherboard for the 80486 platform is not easy. There are several criteria or approaches for the implementation of such projects. 1. Consider whether you need PCI slots? 2. The need for VLB slot(s) 3. The need for everything on one board.

Since I set myself the task of assembling the most productive Socket 3 system, the presence of ISA and VLB slots was a secondary matter for me, PCI slots were a priority due to their speed characteristics. The fastest chipset was required from the motherboard – this is the UMC 8886/8881. Revisions of this chipset were later used in Socket 5 Pentium motherboards that supported FSB 60/66 MHz and higher. The board must have 4 slots for RAM with support for EDO RAM, the minimum total size is 128 MB (4x 32 MB).

The total size of the L2 cache should be equal to 1 MB, so the motherboard should contain 8 sockets for such microcircuits.

Due to the use of different processors with different input voltages, the board must support a choice of voltages from 3.3 V to 5 V in small steps, in order to be able to “smooth” overclocking. Accordingly, the overclocking capability on the bus from 33 to 50 MHz and higher should be implemented. So which board do we end up with?

Read More »

Posted in:
Boards and Systems

February 21st, 2021 ~ by admin

The 486 CPU Era – The Birth of Overclocking. – Part 1

Introduction

486 CPU Era – the birth of Overclocking – this is how I decided to call everything that was in the pre-Pentium era, which I did not find and become familiar with until a couple of months ago.

(Another Article in cooperation with max1024 of Belarus – Edited/Expanded by Me)

If we abstract from the very first Pentiums, which appeared using Socket 4 in two speeds of 60 and 66 MHz, then these processors won popular fame and love in motherboards based on Socket 5 and 7. Such machines could be seen in the early 90s on which while playing C&C, Warcraft and other RTS games. The Sega Mega Drive II and Super Nintendo game consoles competed with expensive computers. Moreover, the consoles were far ahead in popularity (and to be honest, the graphics and game play were better) and I got used to the joystick much earlier than to the mouse and keyboard.

The question arises, what was there before all these Pentiums? And the answer, if you dig deeper, can discourage or even confuse any inveterate computer enthusiast, since the cultural layer of “hardware” from the very first processor belonging to the x86 architecture to the first representatives of the superscalar architecture is much larger than from the Pentium 4 to the freshly released Intel Core i9-11900K, which belongs to the Rocket Lake family of 11th generation Intel Core processors. It is not so easy to digest this entire historical layer, so I have outlined the framework for myself.

To simplify the chosen concept, I decided that the platform should in any case support the PCI interface, since it is, firstly, relatively fashionable and “modern” and, secondly, gives more room for my experiments with the accumulated PCI expansion cards. I did not impose other, special requirements on the test platform, except that according to the established tradition, it should be the most powerful and fastest set that is possible to assemble.

Here I think some of the readers of this article the “True oldies” will say: “what is this nonsense, where is the ISA, VLB and 8-bit only?”, But everything has its time, we will gradually dive into the depths of the prehistoric hardware sea, otherwise decompression cannot be avoided. [Editor’s note, I grew up on an 8-bit 8088 and of course connected the PC Speaker to a 100 Watt Stereo Amp, the loudest 8-bit beeps ever]

typical VLB videocard – V7 Mirage P64 on S3 Vision 864, 2 Mb (before they hid all the good stuff with a heatsink)

So, let’s play from the presence of the PCI bus, which appeared just during the heyday of 4th generation processors, “fours” or simply – four hundred and eighty-sixths, which first appeared back in 1989 or today it is 32 years ago. “Almost like yesterday” the oldies will say, “We were not born yet,” the rest will answer, although this is not the point.

The previous generation of 386 processors was content to exchange data with peripheral devices more often at the “width” of 8 and 16 bits, although the entire generation of processors belongs to the first microprocessor architecture supporting 32 bits, but despite this, motherboards designed for them had no  32-bit PCI bus. Although this could not have happened historically, since the specification is new, in relation to the previous buses, it (PCI) was first implemented in 1992. This means that the whole choice comes down to the whole variety of 486 processors, and there was enough variety in those years, not that today there is a choice between “red” and “blue”.

Read More »

Posted in:
Boards and Systems

January 26th, 2021 ~ by admin

The Story of the Soviet Z80 Processor

Before we get into the fascinating story of the Soviet (specifically the Angstrem) Z80 clone it’s good to understand a bit about the IC industry in the USSR.  There were many state run institutions within the USSR that were tasked with making IC’s.  These included analogs of various western parts, some with additional enhancements, as well as domestically designed parts.  In some ways these institutions competed, it was a matter of pride, and funding to come out with new and better designs, all within the confines of the Soviet system.  There were also the various Warsaw Pact countries (BulgariaCzechoslovakiaEast GermanyHungaryPoland and Romania), that were aligned with the USSR but not part of it.  These countries had their own IC production, outside of the auspices and direction of the USSR.  They mainly supplied their own local markets (or within other Warsaw Pact countries) but also on occasion provided ICs to the USSR proper, though one would assume an assortment of bureaucratic paperwork was needed for such transfers.

This resulted in some countries developing similar devices, at rather different times, or different countries focusing on different designs.  East Germany was all in on the Z80, Romania, Poland and Czechoslovakia made clones of the 8080, Bulgaria, the 6800 and 6502. They were though, seperate from the USSR’s own institutional system, so while East Germany had a working Z80 in the early 1980’s the USSR did not.  It is this distinction we will focus on today

This article is largely from guest author Vladimir Yakovlev, translated from Russian, and edited/expanded by me.

By the end of the 80s – beginning of the 90s, clones of the British Sinclair ZX Spectrum computer, a simple, cheap computer with a huge library of games originally released in 1982, were being distributed in the USSR. The “strapping” of the central processor instead of the original ULA microcircuit was done on small logic microcircuits of the 555 (74LS) series and the like, but the Z80 itself had to be bought from abroad. Naturally, the thought arose, to start making the processor yourself. After all, the processor itself, developed in 1976 for the microelectronic industry, was not too complicated.

In 1990, the development of an analogue of the Z80 was organized in Zelenograd near Moscow at the Scientific Research Institute of Precise Technology (NIITT) and the “Angstrem” plant. Initially, Zelenograd was conceived as a center of the textile industry, but was later reoriented to the development of electronics and microelectronics by Nikita Kruschev after he visited Silicon Valley (California, USA) in 1959. To this day, Zelenograd has retained the status of a scientific center and the informal name “Russian Silicon Valley”.

The chief designer was appointed Yuri Otrokhov, who had previously led similar developments. Otrokhov, who served as a tanker in his youth (military service being mandatory in the USSR), called the project the T34 microprocessor.

Otrokhov: “T-34VM1 is the internal designation of the KR1858VM1 processor, assigned by me at the stage of development and production in honor of my first tank, on which I learned to drive.”

Here is one of the versions of the creation of the clone, outlined by one of the employees of NIITT at that time, Boris Malashevich [1]:

“Otrokhov, like his colleagues in the department, knew how to develop original microprocessors, but they had not yet had to reproduce analogs. Therefore, the developers included specialists from NIITT divisions who are able to restore the electrical circuit of the IC according to its topology. For 9 months after four iterations, they managed to make an NMOS microprocessor T34VM1 (KM1858VM1, KR1858VM1) – a complete analogue of the Z80A microprocessor, to be made using a 2-micron technology” (The original Zilog version was on a 4 micron process).

While Otrokhov and his team worked at Angstrem to make a NMOS Z80, a similar team was working at ‘Transistor’ in Minsk Belarus to make a CMOS version, later known as the KR1858VM3.

Due to the incredible popularity and demand for the Z80, many analogue manufacturers worked without a license, so in total less than half of all Z-80 produced were licensed products from Zilog or its official partners (SGS, Mostek, etc).

From an interview with the creators of the Z80 [2]:

Faggin: Yes, we were concerned about others copying the Z80. So I was trying to figure what we could
do that that would be effective, and that’s when I came across an idea that if we use the depletion load
the mask that doesn’t leave any trace, then I could create depletion load devices that look like
enhancement mode devices. And by doing that we could trick the customer into believing that a certain
logic was implemented, when it was not. Then I told Shima, “Shima, this is the idea how to implement
traps. Put traps, you know, figure out how to do the worst possible traps that you can imagine,” and then
Shima with his mind, that was steel mind, was able to actually figure out a bunch of traps that he could
talk about.
Shima: I didn’t count [on] talking about that mostly. I placed six traps for stopping the copy of the layout
by the copy maker. And one transistor was added to existing enhancement transistors. And I added a
transistor looks like an enhancement transistor. But if transistors are set to be always on state by the ion
implantations, it has a drastic effect on very much. I heard from NEC later the copy maker delayed the
announcement of Z80 compatible product for about six months. That is what I got from NEC. And finally
a total transistor of Z80 became 8,200 while a total of transistor of 8080 was 4,800.

In the course of the design, due to the fact that the development team had specialists in both the creation of new ICs and the reproduction of analogs, Zilog’s tricks aimed at copy protection were identified and decrypted. For example, the topologist saw the 3-Input-NAND Gate element, but this element worked as 2-Input-NAND Gate. The topology and layout of the resulting clone was different, but the functionality did not differ from the original. At first, it was possible to identify such traps, making sure that the circuit was inoperable, only by examining the circuit elements inside the die using probe analyzers. But, having understood the principle of constructing traps, a mechanism for their detection was also developed. As a result, it was possible to make a full-fledged analog of the Z80, although the electrical circuit and topology of the T34MV1 had some differences.

The German Connection

Read More »

Posted in:
CPU of the Day

January 8th, 2021 ~ by admin

Shanghai – World’s 1st 45nm Monolithic Quad Core x86 CPU – October, 2008

In sports, particularly Baseball, its often said that the longer a record is to say, they less impressive it is.  ‘Most Home Runs Ever’ is much more of an impressive record then ‘Most Home runs in the 7th inning against a left handed pitcher with a runner on 3rd’  Both are of course records, the first, many may even know the answer (Barry Bonds), the second? I’m sure someone can look it up but I have no idea.

So when I got this interesting commemorative AMD Opteron Sample it seems fitting to break down the record engraved on it ‘Shanghai – World’s 1st 45nm Monolithic Quad Core x86 CPU – October, 2008’  That seems impressive, and the reality is that it was (and is) and its a testament to the very hard work the design team, whose names are engraved for perpetuity on the chip, put into it.  The Shanghai was a third gen Opteron that followed the very troubled Barcelona, so it was really a make or break design for AMD.

Intel Core 2 Quad Q9100 QAVK Engineering Sample – Dual 45nm dies – Mid 2008

The most impressive aspect of the record is ‘First monolithic quad core x86 CPU.’  This was putting 4 x86 cores on a single die. Now Shanghai wasn’t the first to do this, as Barcelona had done so previously, thus the addition of ’45nm’ to the record.  Barcelona was made on a 65nm process whereas Shanghai shrank that to 45nm.  At the time Intel had the Quad-Core Clovertown Xeons (65nm) and had (in 2007) just released the Harpertown/Yorkfield Quad-Cores made on a new 45nm process.  All of these used two dual core dies in a single package. Intel was able to catch up later with the Nehalem based processors in 2009.

Was there other single die Quad-cores at the time?  What if we look outside of the realm of x86?  In 2008 IBM released the z10 quadcore processor, it was a single die, running at up to 4.4GHz (!) but it was made on a 65nm process.  Likewise, the UltraSPARC T2 was a 8-core CPU from 2007 but again, only on a 65nm process.  Freescale released the 45nm quadcore, single die P3 series P2040 PowerPC processors, but in 2010.  MIPS had the quadcore 1004K in 2008 but only on 65nm. So it seems AMD may have had a better record then they thought.

What if we stretch what we call a processor? There were at the time some fairly simple large multicores like the Tilera TILE64 (64-basic 32-bit cores) made on 45nm process, but they are less of a general purpose CPU.  Perhaps the closest is the Sony CELL Processor in the Playstation 3, which IBM was moving to 45nm in 2008 and had 1x PowerPC core + 7 SPEs. Perhaps AMD could have made a claim to the first 45nm single die CPU ever, even including non-x86 chips.

 

Posted in:
CPU of the Day

November 20th, 2020 ~ by admin

SEMICON WEST: A Blast from 1996

SEMICON WEST 1996 PLCC68 Memorabilia

In 1970 an industry group was started called SEMI (Semiconductor Equipment and Materials International).  They were formed to represent, as the name implies, all the various people/companies involved in making semiconductors.  This wasn’t so much the Intel’s and AMD’s but the companies that made the equipment, chemicals, and even software they used to actually design, fab, package and test chips.

In 1971 they had their first tradeshow, SEMICON WEST, at San Mateo Fairground, California.  They continue to have events around the world, SEMICON WEST is now in San Francisco (and there was a corresponding SEMICON EAST that started in 1973 in New York, but no longer exists).

SEMI not only provides an avenue for vendors and technology to be showcased, but they also work to put forth standards in industry, as well as education.  It was SEMI in the 1970’s who worked to develop standard wafer sizes, can you imagine if there was no standard sizes for such a principal component? Madness!

Lack of molded markings (usually date/country/lot would be included) suggest this was made specific for the conference.

These conferences have seminars on such compelling topics as ‘Chemical Mechanical Polishing’ and ‘Photosensitive Benzocyclobutene for Stress-Buffer and Passivation Applications.’  Today they also include vendors and information on hiring, and personnel management in the semiconductor industry, as well as safety, environmental, and education.  Certainly not as flashy as CeBIT or COMDEX, but perhaps equally if not more important.

The pictured chip was given away as swag during SEMI/WEST 1996.  Its a pretty typical PLCC68 package with the logo from that years conference.  On the back there is a complete lack of markings (even in the mold) suggesting this may have been a run specifically made for the conference, probably by a packaging vendor.

Posted in:
CPU of the Day

October 21st, 2020 ~ by admin

SSQ22667-001: An 80C186 for the Space Station

Intel SSQ22667-001 SQ80C186-12 – Space Rated CMOS 80186

Recently some interesting CPUs showed up on eBay and other IC selling sites.  They were marked SSQ22667-001 and made by Intel.  Some were conveniently also labeled SQ80C186-12.  Packaged in a 68-pin CQFP package, they typically would be labeled as a MQ80C186 (Military CMOS 186 running at 12MHz) but these were as ‘SQ’ prefix, and had the weird SSQ22667-001 part # on them as well. Others in the same package were marked SSQ22668 and 22669. So what was special about these CPUs? Was this some random House # for an OEM?  Nope, these were made for NASA, specifically to conform with MIL-STD-975.  To learn a bit more about how these MIL-STD’s work, lets take a journey back to the 1960’s (everyone knows hat was a fun time)

Back in the 1960’s integrated circuits were getting to be more standard, and more available. Many companies were making many different types (generally simple logic at the time, but that was changing fast).  The US Military was, of course, an early user of integrated circuits, as they could afford them, and IC’s allowed for some cutting edge technology.   To make purchasing and stocking such components easier, the military, as they usually do, decided there needed to be some standards, and ICs for the military, should be available in higher standards

Intel MC1702A/B – MIL-STD-883 Class B – 1976

then those destined for your microwave oven or digital alarm clock.  Thus in May of 1968 the MIL-STD-883 was released.  This was (and continues to be, its on Rev L now) a standard created on Test methods and procedures for ICs, any IC’s.  It provides such things as inspection methods, burn-in methods, lot sampling, and a whole host of other ways to test and inspect IC’s.  As the years went by, different Classes of testing were added.  A computer chip the captains coffee pot did not need the same testing as a computer chip destined for a nuclear submarine, or one for use in Space.  Several classes were then created for space, S, V, Q and B, varying in the degree of testing needed.  Obviously a vehicle designed to take people to space should use higher quality parts then one launching unmanned missions.

As IC’s continued to be developed, and many devices became ‘standard’ like various RTL/TTL devices and the like, the Military wanted to define those better for themselves as well.  Thus in 1969 MIL-M-38510 was released.  38510, often called JAN38510 (Joint Army Navy Standard Naming which was used through Rev J in 1991) was a General Specification for Microcircuits.  It provided fit, form and function standards for various devices.  They could be made by anyone, anyway they liked, but to be marked/used as a JAN38510 device they had to meet what it defined that device to do.  This was all

Zilog JAN MIL-M-38510 52002BQA Z8002 CPU – 1987

based on existing devices, it simply took a commercial device, such as a 74181 ALU, and gave it a 38510 description and part number.  This ensured that no matter where the Military got that 38510 standard 74181 ALU it would behave the exact same.  The 38510 standard refer’d back to the MIL-STD-883 testing procedures, it in itself did not define any testing.

As things progressed, MIL-STD-883 with the how, and MIL-M-38510 with the what, NASA decided they should have their own standard (American government agencies like to compete).  Based on the 38510 standard,and the 883 testing standards NASA created MIL-STD-975 in 1976.  This was essentially a list of products that met NASA’s standards for all electronic devices.  Everything from capacitors, diodes, cables, oscillators and even some processors. Ultimately this was a great idea at the time.  It provided designers with a list of parts they could use that NASA had already certified as acceptable, rather then having to test/certify every single piece.  The cost and time saving were immense once the initial certification was done.  The list of certified devices was updated every few years through 1994 when the standard was canceled, likely because there was just too much new devices becoming available to keep up with.  Three levels of quality are used in this standard. Grade 1 parts arc very low risk, higher quality and

Illustration of the Ørsted spacecraft in orbit (image credit: DRSI)

reliability parts intended for critical applications (such as man rated space applications). Grade 2 parts are low risk, high quality and reliability parts for usc in applications not requiring Grade 1 parts. Grade 3 parts are higher risk, good quality and reliability parts but are not recommended for applications requiring high product assurance levels.

These particular SQ80C186s are made by Intel and listed as Grade 3 devices.  This is mainly because Intel decided not to take part in the NASA certification process, so their grading is based on their MIL-STD-883 QML (Qualified Manufacturer List) testing.  These parts were used on many satellite designs (such as PoSAT-1, Portugal’s first satellite in 1993 and the 1999-2014 Danish Ørsted Geomagnetic Mission)  as well as the International Space Station.  Its possible on the ISS they were used in a non-mission critical area where Grade 3 is acceptable.   Even as a Grade 3 device the replacement cost (in 2003) was $2,266.  Today they are a mere collectors item, as parts like these need to have a certified traceability with them, knowing where they have been and how/where they were stored is important to them being certified for use. These particular chips were made in 1993, a lot can happen in 27 years of storage and transport around the world.

Read More »

Posted in:
CPU of the Day

September 29th, 2020 ~ by admin

Aircraft Instrumentation, Bitchin’ Betty and an 80C86 CPU

F-15 with P4 Instrumentation Pod – Looks like a missile under the wing, with blue and red stripe.

Quite the combination I know, but of course all related.  Last week I got some boards in that were quite interesting.  They were all fairly early serial numbered, from the 1980s and military in design.  Now one thing about anything military is identifying it is pretty hard to do, especially when it hails from an era before the Internet.  Many records from the 1980s have made it online, but OCR and transcription errors abound, a single wrong digit can turn an item made for a A-4 Skyhawk into a new blade from a lawnmower or a shiny new Navy mess tray.

Thankfully these boards all had a CAGE code which the US uses to identify each and every supplier.  In this case that code was 94987 which is Cubic Defense.  Cubic didn’t make lawnmower blades or mess trays but they did make a lot of instrumentation systems for aircraft (and they continue to do so).

F-16 with blue training pod under its left wing)

It turns out that training fighter pilots is best done without having to use live weapons, for obvious reasons, but in all other aspects should remain as true to lifer as possible, and then be able to be analyzed after that fact in order to learn from mistakes, and see who gets bragging rights for pulling the most G’s.  This means that the aircraft has to send and receive data as it would in combat, threat warnings have to go off when targeted, missiles have to be ‘launched (while being captive) at the appropriate times, and every aspect of the flight must be recorded, speed, roll rates, altitude, etc.

Cubic made pods, that attached to one of a fighters weapon hardpoints (typically the outermost) that did exactly that.  These pods interface with the aircraft’s flight systems (using the standard 1553 bus) as well as with ground based systems on the training range, forming a complete picture of what is going on between all the aircraft taking part.  These particular boards are from Cubic’s second generation digital pods, the P4 series (the first gen was, the P3). Specifically the P4A series.  Each pod contained a vast amount of sensors, antennas and instrumentation to monitor and record what was happening, as well determine if a missile as ‘launched’ to or from the fighter.

Cubic 185200-1 with Harris ID80C86 – The brains of the AN/ASQ-T25 P4AM Training Pod

At their heart was a Harris or Intel 80C86 processor, (Harris actually did the CMOS conversion on the 8086).  This is one of the earliest applications of the CMOS 8086.  In this case the 80C86 is running off of the normal 8284A clock generator and a 13.5MHz crystal. This results in a processor frequency of 4.5MHz, a bit under its 5MHz rating.  This is pretty typical of military applications, it generates less heat, draws less power, and gives more margins.  This particular board has a industrial spec CPU, later production versions had a full military qualified part (this board was a prototype).

Read More »