POWERPC 602 - A LOOK UNDER THE HOOD

(February 17th 1995) Although we have previously described the
PowerPC 602 as an 'embedded' processor, neither Motorola nor IBM
chooses to describe it as such. In fact it is something of a hybrid
chip, straddling the increasingly hazy line between general purpose
and embedded processors. The 602 is unlike any of the other PowerPCs
we have seen so far - it's not as stripped-down as the companies'
embedded offerings, it also lacks their integrated glue logic, but it
twists the standard PowerPC architecture in innovative ways, to suit
it to the personal digital assistant and graphical markets.

To get the vital statistics out of the way, the chip has 1 million
transistors, measures 7.07mm square and has four functional units -
integer, branch, load/store and a single precision floating point
unit (FPU). Unlike the other Somerset-designed PowerPC parts,
dual-precision floating point will have to be carried out in
software. This is why there is no estimated SPECfp number for the
602. Power saving modes are essentially identical to the PowerPC 603,
so individual modules can be switched off when they are not in use to
save power. At 66MHz the chip is expected to use less than 1.2 Watts,
dropping to 2 milliwatts when on standby.

Let's start with the bits of the chip that have gone missing,
compared with the 603. As previously mentioned, the FPU is only
single precision. In addition the load/store unit has been trimmed
back by trapping some of the more complex operations such as graphics
and string moves - these have to be handled by separate software
routines, if required. The instruction control unit has also been
simplified so that the chip can only dispatch one instruction at a
time. The size of the cache has been cut back to 4k, two-way
associative.

But to the naked eye, the most obvious difference is the die size and
the number of pins sticking out of the thing. The average desktop
processor has separate data and address pins, the 602 design team has
done away with this to keep things small, instead multiplexing both
sets of information over the same set of lines. By reducing the
number of simultaneously switching pins, power consumption is cut.
Piping both addresses and data over the same wire has obvious
performance implications, but the team claims this will not be a
problem because the multiplexing scheme chosen "still outperforms
most of today's memory subsystems using 70ns DRAM". Still, it is
amusing to recall the first announcements of the chip when it was
trumpeted that 3DO would be using a "64-bit PowerPC". IBM and
Motorola subsequently clarified this, saying that the "64" referred
to the data bus, rather than the width of the internal registers. Now
it turns out that even this data-bus is a shared, multiplexed affair.

>From the description so far, it might sound as if the 602 is a
hacked-about 603, so onto the additions, most of which are cunning
little touches, designed to aid performance in particular target
markets, without taking up much silicon. For example, the integer
unit (described as the "fixed point" unit by the 602's design team,
for no discernible reason) can multiply a byte of data by a word of
data every cycle: good in graphics and compression applications,
where data is frequently presented as a byte-stream, according to the
team. Similarly, the integer unit can add data items in logarithmic
form, without having to have them decoded first - good for DSP-type
things such as handwriting and speech recognition, say those close to
the design team.

Going back to the issue of 3DO's involvement with the 602, and the
initial announcement that the multimedia company had strongly
influenced the chip's design. Evidence of that is hard to find today
and the IBM and Motorola people we have spoken to talk about a more
general, advisory role. However they do point at the 602's unique
"Protection-Only" memory mode, designed to protect the system from
badly behaved software, with minimal overhead.