MAVEN to Mars – RAD750 Powered

NASA has successfully launched the $671 million MAVEN mission to Mars for atmospheric research.  Like the Mars Reconnaissance Orbiter it is based on, it’s main computer is a BAE RAD750,  a radiation hardened PowerPC 750 architecture.  This processor first flew on the Deep Impact Comet chaser and is capable of withstanding up to 1 million rads of radiation.  The entire processor sub-system can handle 200,000 rads.  To put this in perspective, 1000 rads is considered a lethal dose for a typical human.  Likely much higher then a Apple Mac G3 that the PowerPC 750 was originally used in back in 1998 as well.   The processor can be clocked at up to 200MHz though often will run slower for power conservation.

The MAVEN should reach Mars within a few days of the Indian Space Agency’s $71 million Mangalyaan Orbiter launched earlier this month.  MAVEN is taking a faster route, at the expense of a heavier booster and larger fuel consumption.  The Mangalyaan Orbiter’s main processor is the GEC/Plessey (Originally produced by Marconi and now Dynex) MAR31750, a MIL-STD-1750A processor system.

Itanium Sales Forecasts vs Reality

‘Itanium is dead’ is a phrase that has been used for over a decade, in fact many claimed that the Itanium experiment was dead before it even launched in 2001.  The last hold-out of the Itanium architecture was HP, likely because the Itanium had a lot in common with its own PA-RISC.  However HP has announced that they will be transitioning their NonStop sever series to x86, presumably the new 15-core Xeons Intel is developing.  Itanium was launched with goal of storming the server market, billed as the next greatest thing, it failed to make the inroads expected, largely due to the 2 decades of x86 code it didnt support, and poor initial compiler support.  Many things were learned from Itanium so though it will become but a footnote, its technology will live on.

Interestingly other architectures that seemed to be n the brink are getting continued support in new chips.  Imagination, known for their graphics IP, purchased MIPS, and now has announced the MIPS Warrior P-class core.  This core supports speeds of over 2GHz, and is the first MIPS core with 128 bit SIMD support.

Broadcom, historically a MIPS powerhouse, has announced a 64-bit ARM server class processor with speeds of up to 3GHz. Perhaps ironic that ARM is now being introduced into a market that Itanium was designed for. Broadcom has an ARM Architecture license, meaning they can roll their own designs that implement the ARM instruction set, similar to Qualcomm and several others.

POWER continues to show its remarkable flexibility.  Used by IBM in larger mainframes in the POWER7 and POWER8 implementations it crunches data at speeds up to 4.4GHz.  On the other end of the spectrum, Freescale (formerly Motorola, one of the developers of the POWER architecture) has announced the 1.8GHz quad-core QorIQ T2080 for control applications such as networking, and other embedded use.  These days the POWER architecture is not often talked about, at least in the embedded market, but it continues to soldier on and be widely used.  LSI has used it in their Fusion-MPT RAID controllers, Xilinx continues to offer it embedded in FPGAs and BAE continues to offer it in the form of the RAD750 for space-based applications.

Perhaps it is this flexibility of use that has continued to allow architectures to be used.  Itanium was very focused, and did its one job very well. Same goes for the Alpha architecture, and the Intel i860, all of which are now discontinued.  ARM, MIPS, POWER, x86 and a host of MCU architectures continue to be used because of their flexibility and large code bases.

So what architecture will be next to fall? And will a truly new architecture be introduced that has the power and flexibility to stick around?

nCube/2 Processor – 20MHz
The logo is a Tesseract – a 4-way Hypercube

In 1983 Stephen Colley, Dave Jurasek, John Palmer and 3 others from Intel’s Systems Group left Intel, frustrated by Intel’s seeming reluctance to enter the then emerging parallel computing market.  They founded a company in Beaverton, Oregon known as nCube with the goal of producing MIMD (Multiple Instruction Multiple Data) parallel computers.  In 1985 they released their first computer, known as the nCube/10.  The nCube/10 was built using a custom 32-bit CMOS processor containing 160,000 transistors and running initially at 8MHz (later increased to 10).  IEEE754 64-bit floating point support  (including hardware sqrt) was included on chip.  Each processor was on a module with its own 128KB of ECC DRAM memory (implemented as 6 64k x 4 bit DRAMs.)  A full system, with 1024 processor nodes, had 128MB of usable memory (160MB of  DRAM counting those used for ECC).  From the outset the nCube systems were designed for reliability, with MTBFs of full systems running in the 6 month range, extremely good at the time.

The nCube/10 system was organized in a Hypercube geometry, with the 10 signifying its ability to scale to a 10-way Hypercube, also known as a dekeract.  This architecture allows for any processor to be a maximum of 10-hops from any other processor.  The benefits are greatly reduced latency in cross processor communication.  The downside is that expansion is restricted to powers of 2 (64, 128, 256, 512 etc) making upgrade costs a bit expensive as the size scaled up.  Each processor contained 22 DMA channels, with a pair being reserved for I/O to the host processor and the remaining 20 (10 in + 10 out) used for interprocessor communication.  This focus on a general purpose CPU with built in networking support is very similar to the Inmos Transputer, which at the time, was making similar inroads in the European market.  System management was run by similar nCube processors on Graphics, Disk, and I/O cards.  Programming was via Fortran 77 and later C/C++. At the time it was one of the fastest computers on the planet, even challenging the almighty Cray.  And it was about to get faster.

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