Anandtech and Chipworks deconstructed an Apple A8 processor, the hear of the new iPhone 6.  By their analysis it is not a radical departure from the A7.  It includes a slightly upgrade, but still quad-core, GPU, and an enhanced dual core ARM processor.  The focus here is clearly on battery performance rather then sheer speed.  Perhaps most interesting is the move from Samsung’s 28nm process to TSMC’s 20nm process (Being made by TSMC will hopefully put to rest the rumors of an Apple/Intel tie up once and for all.).  This results in lower power, a smaller die area, and, assuming yields are on par, a lower cost per chip.  Clock speed appears to be close to the same as the A7 at around 1.3GHz, with most performance improvements being architectural. It would appear to be the smallest improvement in the Apple A series, certainly since the A4->A5.

Considering the incremental improvement from the A7, one can only imagine what Apple has in mind for the A9 which is no doubt well under development.

National Semiconductor MM5782N – 400KHz 1976

In August we detailed the COP2404 and the COP400 line of 4-bit microcomputers by National Semiconductor.  This NMOS design originated in 1977 and was made for over 30 years.  It, however, was not the the first COP line of National Semiconductor.  In fact the COP400 family was referred to as the COPS II for a brief period in the 1970’s.  If the COP400 was the second in line then what was the ORIGINAL COP microcomputer?

That would be the COPS I of course, better known as the MM5781/2 and its derivatives, the MM5799, MM57140 and MM57152.  These microcomputers were released in 1976 and were made on a volume PMOS process.  They were designed to be inexpensive and simple to use.  The design of the 5781/2 actually started with the MM5734 which was a single chip accumulating calculator chip.  The differences are not as big as one may think.  A multi-function calculator with memory needs an ALU, registers, ann accumulator and instruction decoding, as well as very limited memory and fairly extensive I/O (to run the display and read inputs from the keyboard).  National saw this as an opportunity to capture a bit of the low-end market.  They already had the IMP-16 for their high end, the SC/MP for the mid range, as well as second sourced Intel MCS-4 and MCS-80.  What they lacked was something to compete with the likes of the WD1872 and the TI TMS1000 series as well as the rise of the Japanese 4-bit solutions from NEC, Toshiba and Sanyo.

The 5781/2 was a 2 chip solution, together they formed a microcomputer.  The 5781 contained the program ROM (2048 x 8 bits), as well as the program counter and some control logic.  The 5782 was contained the full ALU, the accumulator, the instruction decoder, and 160×4 bits of RAM.  It could execute 33 different instructions.  Clock speed was 70-400KHz and was provided by an off-chip oscillator.

National Semiconductor MM5799 – Single chip COPs

National combined the 5781/2 into a single 28 pin chip called the MM5799.  It contained all the logic of the 5781/2 but with a smaller amount of RAM (96 x 4 bits) and ROM (1500 x 8 bits). Clock speed remained the same but the instruction set was expanded slightly to 41 instructions.  Two other versions were also made that had more extensive I/O.  The MM57140 which had build in LED drivers, and the MM57152 which was the same, but had built in fluorescent display drivers (this was the 1970’s after all). The ‘140 and ‘152 had 36 instructions 55 x 4 bits of RAM and 630 x 8 bits of ROM. Maximum clock speed was also reduced to 280KHz.

Read More »

MasPar PE3232 – 32 12.5MHz 32 bit Processing Elements – 1992

In the 1980’s DEC researchers were designing a supercomputer based on the Goodyear MPP from 1983.  Jeff Kalb was in charge of the division of DEC involved in this work.  The original Goodyear MPP wa based on a 1-bit processor element (PE).  DEC increased that to a 4-bit PE as well as increased the connectivity between PE’s.  When DEC decided to not commercialize the supercomputer design Kalb left (with DEC’s blessing) to start a company of his own that would.  Thus the creation of MasPar in 1987.

MasPar derives its name from the product it sought to create, a Massively Parallel supercomputer.  These type of computers, also referred to as vector processors are SIMD machines, Single Instruction, Multiple Data.  They perform the same operation on a very large set of data.  SIMD instructions are now found on most all desktop processors, where they can greatly speed up processing of multimedia.  In the late 1980’s there was several companies making such MPP computers.  Perhaps the most famous was Cray, but there was also Thinking Machine’s Connection Machine, Intel’s Paragon (i860 based), nCUBE’s hypercube, Meiko Scientific’s CS-1 (Transputer based) and several others.  Such systems cost from upwards of $100,000 each so sales were not vast, typically companies sold a few hundred to a few thousand systems.

MasPar’s first design, the MP-1 was based directly on the research done at DEC.  Each processing element contained a 4-bit ALU, a 1-bit logic unit, a 64/16 (mantissa/exponent) unit for handling floating point.  Each PE also had 48 32-bit registers.  There were designed as a 32-bit RISC processor, which means, that with the 4-bit ALU, any ALU operation would take at least 8 cycles.  This was considered acceptable in a MPP type system.  Each custom VLSI CMOS MP-1 chip contained 32 individual PE’s.  They were made on a 1.6u process and contained 400,000 transistors.  Clock speed was a fairly low 12.5MHz but this allowed the chips to be air cooled with no special cooling systems.   They were packaged in an inexpensive 208 PQFP, nothing special needed due to the low heat dissipation.  A 1024 PE board (32 chips) dissipated only 50 Watts, and an entire 16k processor system dissipated less than 1,000 watts.

Read More »