Makings of a Comet: The VAX 11/750

DEC 608B 19-14682-00 VAX750 ALP – 4- bit slice

In the mid-1970’s DEC saw the need for a 32-bit successor to the very popular PDP-11.  They developed the VAX (Virtual Address eXtension) as its replacement.  Its important to realize that VAX was an architecture first, and not designed from the beginning with a particular technological implementation in mind.   This varies considerably from the x86 architecture which initially was designed for the 8086 processor, with its specific technology (NMOS, 40 DIP, etc) in mind.  VAX was and is implemented (or emulated as DEC often called it) in many ways, on many technologies.  The architecture was largely designed to be programmer centric, writing software for VAX was mean to be rather independent of what it ran on (very much like what x86 has become today).

The first implementation was the VAX 11/780 Star, released in 1977, which was implemented in TTL, and clocked at 5MHz.  TTL allowed for higher performance, but at the expense of greater board real estate as well as somewhat less reliability (more IC’s means more failure points). It also cost more, to purchase, to run, and to cool.

DEC followed the Star with the 11/750 Comet in 1980.  This was a value version of the Star.  It ran at only 3.12MHz (320ns cycle time) but introduced some new technology.  Part of the ‘value’ was a much smaller footprint.  The TTL had been replaced by bi-polar gate arrays.  Over 90% of the VAX architecture was implemented in the gate arrays, and there was a lot of them, 95 in a complete system with the floating point accelerator (28 arrays).  The CPU and Memory controller used 55 while the Massbus (I/O) used an additional 12 gate arrays.  The 95 gate arrays though replaced hundreds of discrete TTL chips.  And as a further simplification they were all the same gate array.

VAX 11/750 ALP – Contacts run on either edge

Each gate array contained 400 (2 transistor) 4 input NAND gates, and 44 transceiver gates (one for each I/O pin).  They were factory programmed to be any one of the 39 different types needed for a 11/750.  Each was packages in a 48 lead DIP-like flat pack.  Max power dissipation was 2W per ship and they required only two power supplies (5V and 2.5V).  Die size was a relatively small 33.8mm².  This allowed for near commodity manufacturing, further lowering prices.

The heart of the Comet was the Data Path Module.  This consisted of the scratch pad registers, control logic, the ALU, and the superrotator (a 32-bit rotator which handling all rotates and bit shifting.  The ALU was built using 8 identical gate arrays.  Each was configured as a 4-bit processor slice (much like an AMD Am2901, which later VAX implementations would use.  Each gate array was labeled for easy maintenance if needed.

The 22 gate arrays that make up the Comet Data Path are:

608B – ALP – 4-bit Arithmetic/Logic Processor slice (x8)
610B – CCC – Condition Code Chip
612B – CLA – Carry Look Ahead
613B – SRM – 8-bit Super Rotator slice (x4)
614C – SRK – Super Rotator Control
615B – ALK – ALP Control
616C – SPA – Scratch pad Address Control
617C – SAC – Service Arbitration and Clock
620A – TOK – Interval Timer
621C – MSQ – Micro-Sequencer
622B – IRD – Instruction Register Decode
629C – PHB – Status/next instruction logic

Memory Interconnect Module (18 Gate Arrays)

607B – MDR – Memory Data Registers (x8)
609E – ADD – Address Chips (x4)
623C – CAK – Cache Control Chip
624E – PRK – Prefetch Control
625B – ACV – Access Violation
626B – ADK – Address Control
627B – CAK – CPU Memory Interconnect Control
628B – UTR – Microtrap Monitor

Unibus Interface Module (8 Gate Arrays)

611B – CON – Console interface (x2)
618C – UDP – Unibus Data Path (x4)
619D – UCN – UPD Control
630B – INT – Interrupts

DEC 78032 GD-DC333R MicroVAX VLSI

The Floating Point Accelerator contains additional Gate Arrays, and there are a few others not detailed here, but most all are covered.  With only 400 gates to work with, the VAX architecture had to be divided over many arrays, it was still an improvements over discrete TTL which offers only a handful of gates per chip.

In 1982 DEC released the VAX 11/730 Nebula, which was similar to the 750 but based on a commercial 4-bit slice processor (the 2901).  In 1984 DEC Released the VAX 8600, which was the replacement to the 11/780.  It was implemented in Macrocell Arrays (enhanced Gate Arrays) in ECL.  The lower end was handled by the newly released MicroVAX, a 2 chip, VLSI implementation of the VAX architecture.  Development of VAX continued into the 1990’s with many fault tolerant designs made for the military as well.  By 1992 DEC had released the Alpha which slowly replaced the VAX.  However many VAX computers will remain in operation, including in the former Soviet Union, where the VAX architecture was cloned, and used, extensively.