Fujitsu to take ARM into the realm of Super

Fujitsu MB86900 – Original SPARC Processor from 1987 – 14.28MHz

Back in 1987 Fujitsu was one of the founders of the SPARC RISC architecture.  The very first SPARC processors were built by Fujitsu, and used in their servers through the 1990’s and 2000’s. SPARC processors were first used in the CM-5 Thinking Machine in 1991 using 1024 SPARC processors (later upgraded to SuperSPARCs).  Fujitsu began making supercomputers based on SPARC in 1992 with the AP1000 and its UltraSPARC based successor the AP3000.  One of their latest, the K machine, is a 705,024 core 12MW SPARC64 VIIIfx based design that ranks as #5 on the Top 500 Supercomputer list.

This is why its a surprise to many that they have announced the successor to the K Machine will be similar in topology, and will be RISC based, but will not be SPARC based, rather Fujitsu has been working with another well known RISC architecture with serious HPC aspirations, ARM.  Fujitsu has been an ARM architecture license holder for some time and the post-K machine will be based on the 64-bit ARMv8 architecture.  ARM has been working hard to make their chips appeal to the datacenter environment, with some success.  Their low power consumption makes them ideal for high density applications, which a super computer needs.  Estimated performance is 1,000 Peta FLOPS and it is due to go into service in 2020. A speed that would eclipse another recently announced RISC supercomputer….

Sunway TaihuLight (Photo : JACK DONGARRA)

The Chinese recently debuted their own indigenous supercomputer.  Previous Chinese supercomputers (such as the Tianhe-2) had been based on the Intel Xeon series of processors but recently the political climate has shifted, resulting in a ban on sales of these high end chips to the Chinese (ironic since many of them are assembled there).  The TaihuLight is based on the  SW26010 multi-core RISC processor.  This is also an original Chinese design, based on the  ShenWei RISC architecture.  The ShenWei architecture is inspired by, if not based on the DEC Alpha RISC processor from the 1990’s.  The core’s themselves are fairly small, each compute node has a management core, and 64 processing cores and their are 4 sets of these per physical chip running at 1.45GHz (so 260 cores on a single piece of silicon), but there are a lot of them, 10,649,600 to be exact, resulting in a peak theoretical performance of 125.4 Peta FLOPS making this by far the most powerful supercomputer in the world.