HP 3000 Series 33 – 16-bits 11MHz. They were integrated into the desk, with a 20MB hard drive on the left, and the computer on the right (with a 1.2MB 8″ Floppy Drive)

In 1972 HP introduced the HP 3000 line of minicomputers.  Mini of course meaning they didn’t take up the entire room.  They competed against the likes of the DEC PDP-11 and the TI-990.  Original called the System/3000 (apparently to compare favorably to the IBM System/360) they were renamed the HP 3000.  These were 16-bit computers employing a stack based design,  They had no general purpose registers, all operations operated directly on one of several stacks.  The first models were designed using bipolar discrete logic and ROM for the microcoding.  This allowed for good performance but was expensive and large.  Just the processor for the high end Series III of 1978 was 9 boards.

The Series 33 (and the smaller series 30) were to be cost reduced versions, to slot in between the high end Series III and the newly introduced HP 300 microcomputer.  In order to do this those 9 boards for the processor needed to be greatly simplified.  HP engineers decided to use a processor they had already, the CPU from the HP 300 Amigo.  The HP Amigo was a bit of a disaster for HP, after 5 years of development, including

1AB4-6003 RALU -Silicon on Sapphire – 8000 Transistors

designing an entirely new processor it was a failure in the market, suffering from management and politics more then from a technical standpoint (it was not file system compatible with the 3000 line and that caused some concerns).  After being released in 1978 it made only around $15 million in sales and was canceled after a short time.

Part of that 5 year development was for its 16-bit VLSI processor.  In order to get the speed needed for the HP 300 and at a low price, the pressor needed to be a VLSI design (a few chips rather then a few boards).  In order to fit in a smaller pedestal cabinet it needed to energy efficient and heat efficient as well.  HP’s engineers decided to use a Silicon On Sapphire (SoS) CMOS design, a process HP had some great experience with in the MC2 processor.  SoS is a form of Silicon on Insulator, a manufacturing method that is very common in today’s IC’s (using Silicon Dioxide).  Instead of an IC being made on a pure silicon wafer, the silicon is deposited on a wafer of sapphire.  Sapphire is an excellent insulator which wels reduce leakage currents, as well as spurious currents from such things as radiation.  Radiation tolerance is perhaps what SoS became known for most, but its low power performance was what HP was after in the 1970’s.

Die shot of the RALU with labels.

The processor for the HP 300 was designed into 3 separate IC’s, totaling 20,000 transistors (some documentation says 25,000) and running at a clock of 11MHz.  The processor control unit (PCU 1AB2-6003) chip generates microinstruction addresses that control the other two chips: the register, address, skip, and special (RASS 1AB3-6003) chip and the register, arithmetic, and logic unit (RALU 1AB4-6003) chip.

The PCU contains 5000 transistors and handles the microsequencing, clock generation, and a sub-routine save stack.  Clock generation is interesting as its single phase, and variable.  The PCU can lengthen or shorten the clock period as needed.  If a memory operation needs longer to complete the PCU simply holds the lock period longer.  Data path functions are handled by the RASS and RALU chips.  The RASS contains about 7000 transistors and contains a register file for the second operand to the RALU as well as address generation and skip logic.  The largest of the chips is the RALU.  It handles all of the standard ALU functions as well as hardware multiply/divide.  It also contains 16 registers: 8 general purpose registers, and 8 for address storage.  Together these three chips form the CPU of the HP 300 and consume only 1Watt of power.  The processor is a microcoded design so the actually instruction set resides in ROM, in this case on a separate board.  In the case of the HP 300 this also allowed the I/O processor duties to be microcoded into the general processor, eliminating another subsystem.

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National 2758 – Intel 2758 (1979) – Intel 2758 (1980) – Click for larger version

Recently I got in some nice 2758 EPROMs.  The 2758 was a 5V 8k EPROM and really the first of the standard EPROMs (with industry standard pinouts, voltages, etc).  The original 2708 required 3 supplies (5V, -5V and 12V) while the 2758 required only +5VDC.  EPROMs are particularly nice as due to the fact that they need a window to allow UV light in for erasure, you can also have a clear shot of the die (in most cases).

Two things caught my eye on these 3 EPROM’s.  First, the National Semiconductor 2758 die looked suspiciously like the Intel die.  This isn’t too unusual as National was one of Intel’s primary second sources throughout the 1970’s.  Intel did not have the best fab’s early on so second sourcing was a must.  As a product of this some strange things happened, such as Intel die’s being in National labeled parts (though the reverse is not known to have happened).

Intel 2758 w/ 2716 die

The second thing you can see in the picture is the difference in die structure between the otherwise seemingly same Intel 2758’s.  One has bonding wires on all 4 sides, while the second one has bonding wires only on the top and bottom of the die, and a completely different layout to the die.  My first suspicion was that the Intel and National may both be the same die, so I put them on my scanner (I REALLY need  a microscope). At 4800dpi (or 9600dpi on one) you can see that they are in fact different dies, and both are not 2758 dies….

National 2758 also using a 2716 die

Both are actual 2716 dies! We saw this several years ago with 2708s being used as 2704’s as well as in Soviet designs.  The third die is a 2716 die as well.  All Intel (and National) did was leave one address line unused (tied to ground in this case).  Its likely these dies had a defect so the affected area was effectively disabled by not using that address line.

C2758 S1865 – Defective 2716 die using only the upper 8k

The difference in the Intel dies is also interesting.  Early in the production of the 2716 Intel changed the die layout to increase density. That’s why one die has the bonding wires on all 4 sides and the newer die only on top and bottom (which made assembly faster and more reliable

as well as increasing density).  The 2716 was released BEFORE the 2758, the 2758 being almost an afterthought, it is very likely that ALL 2758 dies are actually 2716 dies, as it would make little sense for Intel to create a separate mask set for a product that was likely to be low volume.  The 2758 data sheet lists pin 19 as A_R (Address reference) and specifies it to be driven low, or for the S1865 driven high.  Pin 19 on a 2716 is A₁₀ so A_R on the 2758 is simply selecting the lower 8k or for the S1865 the upper 8k.  Being as there was 2 versions of the 2758 using different parts of the die, its clear Intel was using defective 2716 die to make the 2758, at least early on.  Later documentation simply has Pin 19 listed as GND.

As a side note, the CPU Shack REALLY needs a microscope, sorry for the blurry photos from the scanner.

GRAPE-6 Processor – 90MHz -2000

Understanding the movements of the stars has been on mankinds mind probably since we first stared into the sky.  Through the ages we can predict where a star or planet will be in the sky in the next few months, years, even hundreds of years, but to be able to predict the exact orbital details for ALL time is rather more tricky.

This helps understand how planetary systems form, and the conditions that make that possible.  It allows us to see what happens when two massive black holes pass each other by, will the merge? will they orbit? will one go rogue?  These are interactions that take millions of years, and thus we need to calculate the gravitational forces very accurately. This isnt a terribly hard problem for two bodies, and is doable for three with little fuss, but for numbers of bodies greater then that, the calculations grow rapidly, on the order of N²/2.

In the late 1980’s Tokyo University began work on developing a computer to calculate these forces.  Every gravitational force had to be be calculated with its effects on every other body in the system.  These results were then fed to a commodity computer for summation and final results.  This made the Tokyo project a sort of Gravity co-processor, or as they called it a Gravity Pipeline, GRAPE for short.  The GRAPE would do the main calculations and feed its results to another computer.

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