CPU of the Day: Tandem CLX 800 – It Takes 2 To Tango
TANDEM CLX 800 Processor – VLSI CMOS 1u process – 16MHz.
Tandem Computers was established way back in 1974, and was one of the first (if not the first) dedicated fault-tolerant computing companies. They designed completely custom computers designed for use in high reliability transaction processing environments. These were used for support of stock exchanges, banks, ATM networks, telephone/communications interchanges, and other areas where a computer failure would result in significant, costly, disruptions to business services. Tandem was started by James Treybig, formally of HP, and a team he lured away from HP’s 3000 computer line.
Tandem computers are designed to do two things well, fail-over quickly when a failed part is detected. This means that if a faulty processor or memory element is found, it can be automatically disabled, and processing continues, uninterrupted, on the rest of the system. The other design element that Tandem perfected was allowing the computer to find and isolate intermittent problems. If a processor or storage element ceases to work, that is relatively easy to figure out, but if a processor is glitchy, causing errors only occasionally, that can be much harder to find and can result in serious problems for the user. This is known as ‘Fast Fail’ and today is a pretty standard concept, find the error, catch it, and prevent erroneous data from ever making it back into the database. Tandem computers were designed from the ground up to be fault tolerant, disks were mirrors, power supplies, busses,
Tandem CLX 600 PCB (click for larger)
processors,all were redundant, but unlike some other systems, components were not kept as ‘hot spares’ sitting idle until something failed. This kept hardware from being ‘wasted.’ Under normal operation if it was in the system, it was contributing to system performance. A failed component then would reduce system performance until it was replaced/fixed, but a customer would not be paying for hardware that served them no purpose unless something broke.
To support these goals Tandem designed their own processors and instruction set architecture know as TNS (Tandem NonStop). The first processors were a 16-bit design call the T/16 (later branded NonStop I) made out of TTL and SRAM chips spanning 2 PCBs. Performance was around 0.7MIPS in 1976. They were a stack based design similar to the HP3000 with added registers as well. T/16 systems supported 2-16 processors. NonStop II, released in 1981, was similar, but supported the occasional 32-bit addressing, increasing accessible memory form 1 to 2MB per CPU and performance to 0.8MIPS.
The 1983 introduction of TXP saw a great performance improvement, up to 2.0 MIPS, but kept the same form factor. The processor was implemented in TTL, with the addition of many PALs and added much better support for 32-bit addressing. In 1986 the NonStop VLX was released, which moved to an ECL based processor. This was a full 32-bit design, running at 12MHz (3MIPS) but still using discrete components and a new bus system as well. This was to be the high end of the NonStop line, it was fast reliable, and rather large. The desire for a more economical system to fit the needs of smaller customers led to a first for Tandem…
The Tandem CLX was the first Tandem computer system to be implemented with a (mostly) single chip processor. The first of the CLX line, the 600 was implemented in 6 CMOS chips, made by VLSI on a 2u process. They ran at 7.5MHz resulting in about 1MIPS if performance, slower of course the the VLX, but they were designed for value not raw speed. The processor consisted of a pair of identical CPUs, running in lock step, each having 60,000 transistors (81,000 sites), a pair of IPBs (inter-Processor Bus) with 19,000 transistors each, and a I/O Controller and Memory Controller (12,000 and 25,000 transistors each). These processor are micro-coded, with some microcode on chip, and the rest stored off chip. It is this extensive micro-coding that helps the processor make up for some of the performance losses associated with less, and smaller busses then the discrete implementations. The smaller busses do significantly lower costs though (less SRAMs needed, and smaller cheaper packaging for the processor. The processor internally is similar to the VLX design, a pair of 16-bit ALU’s are used to implement 32-bit addresses. There is 160 54-bit words of microcode on-chip, which stores a subset of the off chip microcode. Off chip microcode is loaded into 30 16kx4 35ns SRAM chips, providing 14k words of microcode, 2k words of page table cache and 16k words of instruction/data (shared) L1 cache.
TANDEM CLX
In 1989 the CLX processor was redesigned for VLSI’s 1.5u process, resulting in the CLX700. THis increased the clock speed to about 11MHz providing 1.5MIPS of performance. The CLX800, released in 1991 was another performance improvement, again realized by a process shrink at VLSI. The CLX800s processor was now made on a 1u CMOS process at a clock speed of 16MHz. This resulted in the lower end CLX line performing at 2.2MIPS, nearly as fast as the original high end VLX.
The CLX800 and the high end Cyclone (ECL gate array based, 10MIPS) were the very last of the the original Tandem architectures. Tandem moved to MIPS based systems in the 1990’s. In 1997 they were purchased by Compaq, which was then merged with HP in 2002. Interestingly, this brough Tandem computers, which was started by former HP employees, back to HP 28 years later. As part of HP (now HP Enterprise) Tandem computers were moved to Itanium processors, and later x86 processors in 2014. The original TNS kernel was simply ported over, old code translated or recompiled (in the case of MIPS compiled code). Tandem continues to provide fault tolerant computing to customers around the world.
