KP21264 Processor/Architecture Features
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Out-of-order instruction execution
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64KB on-chip data and instruction caches
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Powerful branch prediction through intuitive execution
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High bandwidth for high-speed access to level 2 cache memory and system memory (up to 5GB bandwith for L2-Cache)
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Chipsets supported by more than four leading-edge vendors, uni, dual, quad and 24 or more
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Industry open standard socket - AMD K7 chipset support and Slot A interchageability on the same motherboard
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Scalable architecture based on cross-bar switch chipset implementations
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Supports Windows NT, UNIX, LINUX and VMS
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