In 1974 National Semiconductor introduced what is arguably the first 16-bit microprocessor (it had a 8-bit mode as well which was more efficient but could run 16-bits as well).  This chip was made on a PMOS process and ran at 1.3MHz.  In some ways it was ahead of its time, there wasn’t a ton of demand for a 16-bit processor at the time and interfacing to its PMOS architecture was…tricky.

The PACE used -12V, +8V as well as +5V.  It also required a high power 2 phase clock (the clock drove the internal logic).  National was to use Signetics and Rockwell as second sources but neither ended up making chips.  (this was a 2 way agreement, as National was to second source the 2650 for Signetics and the PPS-4/PPS-8 for Rockwell. The PACE had a 10 level 16-bit stack and 4 16-bit general purpose registers.  It supported 46 instructions.

National Semi. IPC-16A-500D PACE 1977

The PACE found a very few design wins, mostly used in custom applications where its speed and 16-bit were useful.  It was designed into a custom control system for a concrete batch plant, and later (in 1980) used by CERN in Switzerland to control a touch terminal used for particle accelerator experiments (specifically controlling the Modal terminal for the Super Proton Synchrotron).  In this application its speed and its 16-bit capabilities were useful for the math functions needed.  CERN eventually replaced it with the much easier to work with Motorola MC68000 (which had Euro sources available).  A similar use was found by the Australians Dept of Defense to control a graphics terminal also used for physics experiments.

CERN Nodal Touch Terminal – Powered by PACE

In 1977 National converted the design to NMOS, which simplified its interfacing and increased the speed to 2MHz.  This was the INS8900 which required -8VDC, 12V, and 5V but most importantly a normal single phase clock.  The INS8900 also fixed a few bugs, some sources claim the INS8900 also added a NOP instruction, but this  existed officially in the PACE as well (Opcode 5C00). In addition SFLG/PFLG 0000 can be used as a NOP on either processor.

The INS8900 was used in a very early multi-processor system designed by BRATO (British Rail Automatic Train Operation). This system was an early investigation of automating train/track control, and used three INS8900 CPUs to provide enough speed and redundancy to run the 3 programs deemed needed ( automatic driver, tachometer and safety supervisor). Each processor each program (so all 3 processors eventually run all 3 programs) and then the results are compared.  The INS8900 was chosen over the TMS9900 because it utilized the bus much less (the TMS9900 user registers use external RAM, whereas the INS8900 has 4 general purpose internal registers), resulting in less chances of bus interference between the 3 processors.  THe INS8900D was also used in some Sun (not the Sun Microsystems) Motor Testers, used in automotive repair sops in the early 1980’s.

INS8900D – 1979 – Early Production – Large black die cap

INS 8900D – 1985 – Late Production – Small Gold Die cap

These processors are a bit obscure, and as far as I can tell were not used in a ton of products.  They do come up from time to time though, and The CPU Shack now has a test board design available for them.

The board was a challenge to build due to the PACE and the INS8900 having such different voltages and clocks, requiring separate Power Supply Panels to run each.  These are now available for pre-order (we’re not thinking to generally stock these quite yet).

Price is $159 and includes free shipping worldwide. Pre order now and I should be able to ship in around 6 weeks.

If there is enough interest I will of course try to keep 1-2 in stock for that time you find a nice white/gold IPC-16 PACE CPU.

UAE Mars Hope Mission – IR Imager powered by LEON3FT

In the 1990s the ESA began a project to develop their own, open source, easily usable processor for space applications.  Before this the ESA had used mainly MIL-STD-1750A processors, both American made ones, or direct copies their of, such as the Dynex MAS281, a clone of the McDonnel Douglas MDC281.  The ESA explored many different architectures, including the Motorola MC88K RISC process, the MIPS RISC processor, and AMD 29K RISC processor the SPARC, and somewhat oddly, even the National Semiconductor NS32k series processors (which at the time were fairly powerful and used a fair amount in embedded apps).  The SPARC came out of this as the winner.

Cypress CY7C601 SPARC Processor. The basis for the ERC32

At the time the SPARC was a pretty widely used processor, and was being developed by multiple companies.  It was defined as an architecture, and various companies could implement it how they saw fit, in various technologies.  This is very much how the 1750A architecture was made to be as well.  Considering this, the only two really viable architectures that wouldn’t (at that time) have been a sole source item, were the MIPS and the SPARC, both were used and made by many companies, but SPARC it was.

Atmel TSC695 – ERC32 Single Chip SPARC V7 – Still in production

The first implementation was the ERC32 released in 1995, a early SPARC V7 3-chip implementation typically made on a  0.8u process.  These were decent, but took 3 chips, were limited to 20MHz due to memory interface limitations, and were not particularly scalable.  The ERC32 did fly to space, and was used on the ISS as one of the main control computers, as well as 10 other missions including the ESAs ATV resupply vehicles for the ISS.  By 1998 the ERC32 was shrunk to 0.6u allowing it to be integrated onto a single chip (the Atmel TSC695).  This became the standard ESA processor as well as being used by other nations, including China, Israel, India and even NASA.

By the year 2000 the SPARC V7 architecture was rather long in the tooth, having been originally designed back in the 1980’s.  The decision was made to upgrade to SPARC V8.  SPARC V8 added integer multiply/divide instructions, as well as expanded the floating point from 80-bit to 128-bit.  SPARC V8 became the basis for the IEEE 1754-1994 standard for what a 32-bit processor must do.  This was important as it made a very clear definition for software as well, ESA wanted a processor whose support was very well known, and very well defined.  The SPARC V8 implementation became the LEON (for Lion) processor.  These used a 5-stage pipeline (Fetch, Decode, Execute, Memory, Write) and were made on a 0.35u process delivering around 50MIPS at 0.5W. It used around 100,000 gates on a 30mm2 die and was a fully Fault Tolerant design (unlike the ERC32).  It was rated to handle 300Krad of ionizing radiation without upset.

Atmel AT697 LEON2

LEON2 was a fairly similar deign, it moved the MUL/DIV instructions into hardware (instead of emulating them on LEON1) and reduced the feature size down to 0.18u.  It also added many on chip peripherals, such as a PC133 SDRAM controller (with Error detection/Correction) as well as a AMBA bus.  It took around 0.6W at 100MIPS though some implementation saw speeds of up to 120MIPS at 0.3W).  LEON2 saw use on many missions, including the camera controller for the Venus Express mission and the BepiColombo mission to Mercury. LEON2 was designed as a single function processor, but in the real world was often being used as a SoC (System on a Chip).

This led to the development of the LEON3 in 2004.  It was originally made on a slightly LARGER process of 0.20u.  It ran at around 150MIPS at 0.4W.  Its biggest upgrades were moving from a 5-stage pipeline to a 7–stage pipeline (Fetch, Decode, Register Access, Execute, Memory, Exception, Write) as well as supporting multiprocessing.  In realization of the actual use cases the LEON processors were seeing (as SoCs rather then as single processors) the LEON3 added a large array of peripherals.  This included Spacewire, MIL-STD-1553  interfaces, DDR RAM controllers, USB controllers, 1G Ethernet MAC, and much more.  All stuff that originally had to be added on to previous systems was now on chip.

Cobham UT700 Fault Tolerant SPARC V8 LEON3FT

The entire design was good for 400MHz on a 0.13u process and used around 25,000 gates.  Like the LEONs before it, the LEON3 was designed as a synthesizable device.  You could implement the entire core in your on ASIC or FPGA, or buy an FPGA off the shelf already programmed as one (Aeroflex offers this option). You could also buy ready made processors implementing it, much like any other CPU.  Cobham (now known as CAES Cobham Advanced Electronic Solutions) offers the UT700.  The UT700 is a 166MHz processor implementing the full LEON3FT design.  The ‘FT’ stands for Fault Tolerant, and adds a lot of error checking and correcting features on top of the base LEON3 design.  Every bit of RAM on chip, from registers, to cache has error detection and correction.  The UT700 includes 16K of Instruction and Data cache on chip as well as all the usual memory controllers and communication interfaces of the LEON3.  It runs at 1.2-1.8V and and max performance dissipates 4W.

The LEON3FT powers the European Galileo navigation satellites, and many others, including the French Spot-6 Earth Observation craft.  They also power each of the Iridium-NEXT communications satellites that began launching in 2017

Iskra EMZ100E

Back in 1975 the Faculty of Electrical Engineering of the University of Ljubljana (now the Capital of Slovenia, but back then, a city in Yugoslavia) began work with Iskra and AMI to develop an indigenously produced processor.  Iskra (which means ‘Spark’ in Slovenian) began in 1946 and by this time was the largest electronics/telecom company in Yugoslavia.  If it had electrons flowing through it, Iskra likely had something to do with it.  AMI was an American Semiconductor company best known at the time as a contract fab and second source for many other companies.  At the time they were a pretty large 2nd source for Motorola, making 6800 processors and peripherals.

The goal was to co-develop a basic control oriented processor, something that could run basic machines and industrial automation type stuff, toaster oven, games, etc.  It wasn’t meant to be a general purpose computer type processor cranking out spreadsheet formula results.  In many cases the design was to fill the same role as the National Semiconductor COPS400 line.  Iskra hoped to eventually manufacture the processors in Yugoslovia with technology and equipment from AMI, but Yugoslavia and the United States were in a bit of a weird spot in the 1970’s so getting export licenses for fab equipment never happened.  Yugoslavia was rather independent of the Soviet Union (due to the Stalin-Tito rift) which afforded them access to the US that other communist countries of the time didn’t have, but they were still nominally communist.  One has to wonder how hard AMI tried to get such licenses though.

The processor they developed was called the S2000 in the West, and in Yugoslavia, the Iskra EMZ1001.  These processors were made on an AMI NMOS process (most likely 6 micron) with 1200 transistors.  AMI would fab the wafers and ship them to Iskra for final test/assembly.

The EMZ1001/S2000 has been called both a 4-bit and an 8-bit processor. This is because it interfaces to the outside world with an 8-bit databus (and a 13-bit address bus) but has a 4-bit ALU at its core.  Internally it has both a 4-bit bus and an 8-bit bus, and can perform 8-bit arithmetic, just 4-bits at a time.  This of course results in a performance hit, but with a 4.5microsecond cycle time (225KHz) it wasn’t meant to be a high speed chip.  It includes logic on chip to handle timers, and second counting (even a EUR instruction to switch the time base from the 60Hz US standard, to the 50Hz Euro standard) as well as interfaces for buttons, and Capacitive Touch plates and LEDs (S2000) or Vacuum Fluorescent Drivers (S2000A).  It was designed to run on a single 9V supply, making it viable to use off of a 9V battery.

AMI S2000 Dev System (the S6800 Devsystem could also be used )

The S2000/EMZ1001 instruction set contains 51 instructions. all of which are single byte.  49 of these are single cycle instructions.  The processor contains a stack making subroutines and interrupts (on the 2200/2400) easy to handle.  1kx8 of onboard ROM is included (up to 8K total can be addressed) as well as 256 bits of RAM (16x4x4) (which can be used for registers, as well as addresses memory).

Several subversions of the processor were made with different features and some added instructions to handle ADC functions.  The S2200/2400 add an 8-bit ADC and more RAM and ROM (and have 8 additional instructions).

There was a CMOS version as well, the S2210, for lower power applications.

AMI Logo – There was several die revisions that AMI made.

As Iskra was receiving wafers from AMI and was testing them inhouse, they were able to make several temperature ratings.

EMZ1001B 0-55C
EMZ1001C 0-70C
EMZ1001E 0-85C
EMZ1001KCP -40-85C (Industrial/Military Applications)

By the time Iskra was able to begin testing/packaging these, it was 1977-78, and the design was a bit underwhelming for the market. Still it found fairly wide use in Yugoslavia.  The Western equivalents though, are almost never seen making the Iskra version perhaps more common, and widely used.

Omitting the history of the creation of the first microprocessors (such as the 4004) , let’s turn to the moment when 8-bit microprocessors (Intel 8080 and  8085, Motorola 6800 and Zilog Z80 ) firmly conquered the market. It was the time of the second half of the seventies in the last century. It became obvious to specialists that the future belongs to microprocessors, and if you do not invest in these technologies, you will simply fall out of the number of the developed countries. This was well understood by the advisers to the leaders of the USSR at that time. But they also understood that, since the countries of the Eastern Bloc were somewhat late in this work from US, it would be wise to copy the microprocessors already developed overseas. After all, these microprocessors have already solved many of those problems that would take months and years to solve on their own, not to mention huge monetary costs. (It should be noted that the Soviet Union had its own original developments. For example, the 587 series microprocessor kit, this included three microcircuits.)

587IK1	587IK2	587IK3

At that time, it was not clear which chip needed to be copied – Intel, Motorola or Zilog. Each of them was good in its own way, and it was impossible to predict the outcome of the competition between them. In the end, it was decided to copy all microprocessors. And in order not to scatter forces, the enterprises of the USSR were entrusted with copying Intel products. Little Bulgaria got Motorola and Zilog chips were copied in East Germany. This is how Intel, without investing a single dollar, conquered the Soviet market. Microprocessors and microcontrollers under the names 580IK80A (8080A), 1821VM85A (80C85A), 1816VE48 (8048), 1816VE51 (8051)  became native to Soviet electronic engineers.

1821VM85A

The hero of this article is the 1821VM85A-8 bit microprocessor, a functional analogue of Intel 8085A (but in CMOS). It has been developed since the beginning of the 80s at the Novosibirsk plant of semiconductor devices. Production began in 1985. According to Wikipedia, the manufacturing technology is CMOS, 3 microns. According to other sources 0.7 microns, silicone-on-sapphire. Clock frequency – 5 MHz. Theoretically, it can work at a higher frequency.

The die contains about 6500 transistors. When copying the 80C85, several schematic and topological errors were corrected. As a result, the analogue saves stored data without a minimum clock, but the original does not. This manifests itself when the clock frequency changes. When it is reduced to zero, the microprocessor falls asleep, but the contents of all registers remain unchanged. When clocking resumes, the microprocessor continues to execute the program from where it left off.

It was produced in both ceramic and plastic 40-pin DIP packages.

IM1821VM85A – 1990

IKM1821VM85 (tin pins) – 2012

military grade M1821VM85A – 1993

KM1821VM85 – 1991

IKR1821VM85A – 1994

KR1821VM85A – 1996

At the beginning of the marking of microprocessors, the letters I (И), K, M could be used. I did not succeed in finding out the meaning of the letter I (И) in the marking. Sometimes the letter A is missing from the microprocessor name. The letter I (И) is often present in the marking of the chips of the Novosibirsk plant of semiconductor devices. Here is an example of a microcontroller from this manufacturer.

IKM1850VE39 – 80C39 MCU from 1991

Marking the production date on chips was done in two ways. The first is the usual one, consisting of four digits. The first two digits are the year of manufacture, the second two digits are the week of that year. The second marking method corresponds to this table.

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Intel released the i8755 in 1976, the i8755A in 1977 (with better compatibility with the 8085A and 8086/8). The Intel 8755 is an UV- erasable and electrically reprogrammable ROM (UV-EPROM) and I/O chip. The EPROM portion has 16 384 bits, organized as 2048 words by 8 bits. The I/O portion has two general purpose I/O ports, each I/O port is individually programmable as input or output.  These were essentially a combination of the 8255 PIO and the 2716 EPROM on a single die/package. These were made on a NMOS process.

Intel C8755-8 – 1977

Intel C8755A – 1979

NEC D8755AD -1981

Toshiba TMP8755AC ’83

NEC and Toshiba released similar microcircuits behind Intel. Basically, the microcircuit was intended to work together with the 8085A microprocessor. It differs from its predecessor i8080A in that it has a multiplexed data and lower address bus. The standard three-bus architecture of the microprocessor system is obtained by multiplexing with the help of an additional external register. In this register, the low byte of the address is fixed by the special output signal of the microprocessor.

Intel 87C75PF Engineering Sample – 1988

By 1988, the 8755A was obsolete and Intel released the 87C75 instead (see article on the CMOS 87C75).

Novosibirsk IM1821VM85A – 1989

Around this time, the production of an analogue of the i8755A, the 573RF10 microcircuit, began in the Soviet Union. Why start producing a microchip that the world electronics leader is changing to a more advanced one? The fact is that at the beginning of 1988, the production of IM1821VM85A began in the USSR. This was a radiation hard analogue of the CMOS i80C85A. It was with it that the 573RF10 was supposed to work.

K573RF10E (gold pins) 1990

KM573RF10 – Gold ’92 / tin pins ’93

The chip is made in a 40-pin side-brazed ceramic DIP. Supply voltage +5 V. Programming voltage +21 V. It was produced at the Vostok fab in Novosibirsk on a CMOS process (to match the 80C85A).

Unmarked 573RF10

The 573RF10 is the only CMOS chip in the 573 series.

573RF10 die – single memory cell – radiopicture.listbb.ru

Intel 8755A die – 2 memory cells – cpu-galaxy.at

It is noticeable to the naked eye that the 573RF10 is own Soviet development. The 573RF10 and i8755A dies are completely different. The i8755 has two memory arrays clearly visible, while the 573RF10 has only one.
It must be said that the application of the 573RF10 chip was not wide enough. And in general, the idea did not take root. The next obvious step in evolution was the combination of a microprocessor, ROM and RAM, input-output ports in one chip which was frequently done on the MCS-48 and MCS-51 series MCU’s which were also being produced in the Soviet Union at the time.

Written by guest author Vladimir Yakovlev
Edited/Formatted by John Culver – The CPU Shack Museum
Pictures – The CPU Shack Museum and others

This article is about memory chips manufactured by one of the entities – the leader of the electronic industry of the USSR – Angstrem. As you know, the Soviet Union ceased to exist in December 1991. We restrict ourselves to the development period of the considered memory chips produced at Angstrem, the end of 1991. Let’s make an attempt to track how the capacity of memory chips grew, how technologies were improved that allowed the Soviet Union not to let the world leaders in electronics go far from itself at that time. A small example: Angstrem’s Dynamic RAM 4K went into mass production in mid-1975, Intel introduced its own in 1974. Intel launched a 16K DRAM in 1977, and Angstrem released its counterpart in 1978.

Angstrem Headquarters

Angstrem was established in June 1963 in Zelenograd (outside of Moscow) as a pilot plant in conjunction with the Scientific Research Institute of Precision Technology. At Angstrem, new technologies for the production of microelectronics were developed, and pilot batches of new microcircuits were also produced. The debugged production technology was then transferred to other enterprises of the USSR and countries of Eastern Europe.
The development and manufacture of memory chips was one of the main activities of Angstrem. It was on them that new semiconductor structures and production technologies were more effectively worked out, and the stability of obtaining finished products is considered in world electronics as a sign of technology ownership. It’s relatively easy to make a small batch of good chips, it’s hard to make a process whereby a large amount of chips can be made and be reliable. It was the very low chip yield percentage that played a cruel joke on Angstrem when mastering the production process of the DRAM 565RU7 chip.

SRAM

In 1966, Angstrem created the first MOSFET in the USSR, which was the first step towards the strict goal of creating CMOS integrated circuits. The first CMOS microcircuit, created in the Soviet Union in 1971, was the 16-bit Angstrom matrix of memory cells 1YaM881.The supply voltage is 6 volts instead of 5 volts, like the rest of the chips in this series.

1YaM881 – 1972

The next in a series of static RAM chips was the CMOS K561RU2 (K564RU2), released in 1976. 564 series of chips is a “military” analogue of the 561 series. In these series, there are several dozen microcircuits. The chip has an organization of 256 words by 1 bit.

561RU2 die – 16×16 256bit matrix clearly visible – The image is taken from the site https://radiopicture.listbb.ru/ with the permission of the author.

It contains 2067 integral elements. Supply voltage is 3-15 volts. It’s an analogue of CD4061A.  It should be noted that in most cases ‘analogue’ means similar to, not an exact copy or exactly compatible.  The USSR did make some compatible IC’s, but they mostly made stuff that was similar, but built to their own specifications/needs.

K564RU2A -1978

K561RU2 -1979

The package of the K561RU2 chip is wider than the standard packages of this series.

K565RU2 -1979

The K565RU2 static RAM chip was manufactured using NMOS technology. Chip capacity was 1024 bits (1024×1). Contains 7142 integral elements. An analogue of Intel 2102A, developed in 1974. K565RU2 appeared in 1977. It was originally designed to be placed in a ceramic package, but later, in order to reduce the cost of production, the dies began to be packed in plastic packages.

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When Apple bought P.A. Semi back in 2008 it was the beginning of the era of the iPhone, and their was much speculation as to why Apple was buying a company that made low power high performance PowerPC processors.  Especially since the iPhone ran on ARM and the Mac had moved from PowerPC to x86.

P.A. Semi PA6T-1682M

P.A. Semi was started in 2003 by Daniel Dobberpuhl (who passed away in 2019).  Dobberpuhl was one of the truly greats of microprocessor design, with a career starting at DEC on the T-11 and MicroVAX, before helping DEC transition to the Alpha RISC design (21064).  It was Dobberpuhl who started the design center in Pal Alto (where P.A. Semi would later take its name from) that designed the DEC StrongARM processor.  A processor that was later purchased by Intel and became the XScale line of ARM processors.

After Intel bought the StrongARM line, he then helped start SiByte, making MIPS based RISC CPUs, and continued to do so when SiByte was purchased by Broadcom. So when he started P.A. Semi it was less about PowerPC and more about RISC, PowerPC just happened to be the architecture they chose to use.  The design team had extensive experience on a variety of CPU architectures, including SPARC, Itanium, and the early Opterons.  You can see why this acquisition was so attractive to Apple.

PA6T block diagram

In the few years (2003-2008) from when P.A. was founded to when Apple took them over, they did design, market, and sell a PowerPC processor line called PWRficient based on what they called the PA6T core.  The PA6T-1682M was a Dual core PowerPC processor (the 13xxM was the single core version) with each core running at up to 2GHz with 64K of L1 Instruction cache and 64K of L1 Data cache.  They were fab’d on a 65nm process by TI and ran at 1.1V.  The L2 cache was scalable and shared amongst the cores.  In the 1682M this was a 2M 8-way cache with ECC.  One of the most useful features was their clock stepping.  They could drop to 500MHz at only a few watts per core, and then back up to the full 2GHz in 25us.

AmigaOne X1000 (made by Aeon) PA6T-1682M

The PA6T was only on the marked for a few months (from the end of 2007 to April 2008) before Apple bought them for $300 million, but in this time P.A. Semi had numerous design wins.  Amiga selected it for use in the AmigaOne X1000 computer.  The AmigaOne did not hit market until 2011, which means that while P.A. Semi was bought and completely under control of Apple, they still continued to make, support, and supply their previous customers with the 1682M CPU.  Certainly Amiga wouldn’t be big enough to push Apple to continue making a chip?

They were not, but others were, and the PA6T was such a great processor that it had been selected and designed in to many computer system used by US Defense contractors, and if anyone doesn’t like change, its Defense contractors, so with some prodding by the US Dept of Defense Apple continued to make (or rather have TI make) the PA6T processors.  Curtis-Wright had designed the PA6T into their new CHAMP-AV5 DSP VME64 board, which was used for signals processing across numerous military applications.  They also also used the PA6T (at 1.5GHz) in the VPX3-125 SBC. Themis computers, NEC, Mercury and others designed in the PA6T. Extreme Engineering, another maker of PA6T based boards, referred to the design as ‘ground breaking.’

Extreme Engineering XPedite8070 SBC

It would have been interesting to see what P.A. Semi could have achieved had they not been gobbled up by Apple.  Clearly we see the results of the talent of the P.A. team in what Apple was able to accomplish with their A-series processors, but clearly P.A. had something special for the PowerPC architecture as well.

C5M – Ezra-T Prototype Pathfinder – PGA370

Most are familiar with the history of VIA so we won’t dive extensively into that but a quick summary is in order.  VIA was founded in California in 1987 before moving to Taiwan, and previous to 1999 was well known for making chipsets and other support chips for computers.  In 1999 VIA bought both Cyrix (from National Semiconductor) and Centaur Technologies (from IDT, who made the Winchip series of processors.

These purchases did two main things for VIA, it first gave them access to the x86 architecture, and it gave them legal leverage to continue down the x86 road.  Cyrix possessed a license to the P6 processor bus (through a cross licensing with Intel) that was good until 2006.  This allowed VIA to make what became the Centaur based CyrixIII/C3 processor on the P6 based Socket 370 platform. These are the processors and socket we are most familiar with for VIA CPUs.  With clock speeds of 466-1.2GHz and eventual support for the Tualatin based boards these chips were the most ‘public’ facing CPUs.  VIA also of course made many BGA versions, used in ITX form factor, and other mini type systems.

CNA – Isaiah – Interestingly using the old Pentium III-M pin out

The VIA designs, despite originally being called ‘CyrixIII’ were all based on the Centaur designed core.  Intel, as was its custom, sued VIA in 2001 asserting patent infringement, which it is likely VIA was expecting.  As with the case of Intel and Cyrix, VIA countersued, asserting Intel was infringing on patents VIA had acquired with the Centaur deal.  In 2003 a settlement was reached that included a 10 year patent cross license between Intel and VIA and allowed VIA to continue to make x86 compatible processors (extended in 2013 by 5 years until 2018(.  The deal also granted VIA a 4 year (with an extra optional year) license to continue to make chipsets compatible with Intel processors (they had originally signed a deal in 1998 to allow VIA to do so. This is how we continued to get VIA chipset based motherboards for Intel processors.  The deal also added a small detail that leads to todays discussion, it granted VIA a 3 year grace period to continue making bus and pin compatible processors up through 2006.

C5J (Left) and C5R (Right) – Banias Compatible Pentium M pin out

This last part is interesting, the fact that it was a grace period means it reflected what VIA was currently doing, not what they were planning to do in the future.  The obvious example here is the C3 line on Socket 370 using the P6/Tualatin bus, but that was pretty old news in 2003 so what was VIA working on?  CPU’s on more modern sockets of course, namely Socket 479 (mPGA479M) used by the Pentium-III-M (Tualatin) and Pentium M (Banias/Dothan).  These use the same physical socket on a motherboard, but the keying pins are different on the CPUs themselves.  These are all mobile designs which lend themselves well to VIAs low power designs.  VIA did also make several reference boards for these CPU’s so its clear that there was plans for releasing them to the broader market, and likely with additional motherboard support.

C5J (Left) and C5R (Right) – C5R is a 110nm part with a slightly larger die the the C5J

Another socket was just being developed at the time of this agreement, and that is perhaps the most interesting.  Intel LGA775 chips began sampling in late 2003, which is after the grace period of 3 years had begun so it would make sense for VIA to not develop CPU’s using a socket they were going to lose access to in a few years.  The package likely was in development for a couple years prior which is likely why VIA made a few (likely VERY few) samples for it.  The samples are marked C5R which is a C7 Esther core, if VIA’s naming is consistent, this would be the TSMC 110nm version of the 90nm C5J.

C5R With heatspreader and with heatspreader removed.

The Esther core code names are a bit confusing because of how some CPUID programs identify them. X-86-guide.net has a quite nice ID guide that goes into some great detail on them.  In summary there was a 90nm Rev A C5J made by IBM, and later a 90nm C5J (called Rev D) made by Fujitsu with some additional features.  This Rev D part often gets identified as a C5R, or a C5J shrink, neither of which is correct.  The actual C5R (and related C5Q) were what appear to be backup plans for the IBM produced parts, using a larger 130/110nm process at TSMC. Looking at the mPGA479 unfinished packages (labeled C5J and C5R) the die attach area on the C5R is actually slightly LARGER then the C5J (~35mm2 compared to 28mm2 of the C5J)

C5R Esther – 110nm TSMC in LGA775

Most VIA samples are labeled with the code name in Cxx format and not the marketing code name (Esther Isaiah etc) as each of the Marketing code names (for lack of a better term) consisted of many actual sub-cores.

Looking at the table above we can see VIA took many roads in the development of their CPUs, with many that went nowhere.  Some may see this as a lack of direction or focus, but in a lot of ways VIA seemed to be trying to figure out the best CPU for the market at the same time they were trying to make the best CPU from an engineering standpoint.  Where these two paths converged you had a marketable CPU that made it into mass production, and where they didn’t, or where legal road blocks arose, the design was canceled.  VIA’s CPU development is even more obscure now, though they have made a few other designs we will cover in a later article, as well as the return of Intel to the VIA party.

This is turning into a bit of a series on Soviet processors.  Continuing from our article earlier on the 1801VM2 LSI-11.  The 1801VM3 is the further development of 1801VM1/VM2 and is the highest performance microprocessor in 1801 series. It’s a 16-bit single-chip microprocessor that includes an operating unit, a firmware control unit, an interrupt unit, a memory controller and Q-BUS control unit. A distinctive feature of 1801VM3 is a large amount of addressable memory (4MB vs 64K for the 1801VM1 and 64k+64K for the VM2), high performance and ability to connect a floating-point coprocessor 1801VM4.

1801VM2 die

1801VM3 Die

1801VM3 Specifications

• Number of processor Instruction: 72 Fixed Point and 46 Floating Point (with 1801VM4 FPU)
• Address Space: 4MB
• General Purpose Registers: 8
• Manufacturing process: 4 micron N-channel silicon gate MOS technology (later migrated to 3 micron)
• Die size 6.65 × 8 mm
• Transistor count: 28,900 active transistors, 200,000 integral elements
• Clock rate: 4MHz  (1801VM3V) 5MHz (1801VM3B) 6MHz (1801VM3A, upgraded to 8 in 1991)
• Performance: For register based operations (like addition) up to 1,500,000 instruction/s (1.5 MIPS)
• IRQ Lines: 4
• Supply voltage + 4.75V-5.52V
• Power consumption: 1.7-2 W
• Packages: CDIP64 (KM1801VM3) LQFP64 (KA1801VM3) CQFP64 (KN1801VM3/N1801VM3)

Like the VM2 before it the speeds were denoted by a series of dots on the package (or lack thereof)

KM1801VM3A – 6MHz (no extra dot) CDIP64 package from 9008

KM1801VM3B – 5MHz (one extra dot) CDIP64 package from 9003

KM1801VM3V – 4MHz (two extra dots) CDIP64 package from 9202

KA1801VM3 – 8MHz (no extra dot – post 1991) PQFP64 package from 9108

N1801VM3 – 8MHz (no extra dot – post 1991) CQFP64 package from 9324 – Remarked from a military part (rhombus marking marked over)

The KM1801VM3 appeared as part of the DVK line of computers, starting with the DVK-3M model (PCB ”Electronics МС 1201.03” and “Electronics МС 1201.04”).  Using the same ISA (Instruction Set Architecture) allowed DVK (and others) to rapidly update their computer line when new processors were available, and allow for a wider software base.  This is very much like the original IBM PC using the x86 architecture.  The transition from 8086 to 80286 was relatively easy to design, and nearly seamless for the end user.

DVK PCB Electronics МС 1201.03 board on the top.

Many devices built on the basis of the 1801 series CPU contain other microcircuits of the same series (support circuits).
In addition to microprocessors, this series includes:
– ULA 1801VP1-xxx
– masked ROM 1801REх-xxx
– EEPROM 1801RR1

ULA and EEPROM

The 1801VP1-xxx is a ULA- (Uncommitted Logic Arrays). It’s made using a 3 micron N-channel silicon gate MOS technology with one metal layer. First, base silicon wafers are made that contain transistors. These are doped regions of silicon and a separate oxide-insulated layer of polysilicon gates. Then all this is covered with an oxide layer. Base wafers are ready.

In this form, the wafers can be stored for a long time or transferred to another fab. All 1801VP1-xxx chips, regardless of number, have the same structure and arrangement of transistors. And they are made on the same base wafers.

KR1801VP1-22 die

Differences between the chips appear only at the last stage of manufacturing. In the upper oxide layer, the die is etched by photolithography to access the required transistors. And then form a metallic pattern from aluminum. This pattern defines the electrical circuit. The number in the marking identifies the purpose of the chip. For example, 1801VP1-033 is an external device controller.  This is similar to how a MaskROM is made but instead of only memory elements, it contains logic elements allowing for a custom IC to be made (like a mask programmable PAL/GAL)

KR1801VP1-119

The 1801VP1-119 is a companion chip for 1801VM3. It can be said to be the “north bridge“.
The 1801VP1-119 performs the following functions:
-forms control signals for DRAM;
-forms control signals for system SRAM;
-generates signals to select system ROM;
-generates control signals for detection and correction of memory errors (EDC) using Hamming code (555VGH1). Error correction circuits reduced performance by 10-15%. Therefore in some computers, there were jumpers to enable/disable the EDC
-buffer data register control;
-generate other signals

This was the beginning of what would be come chipsets, replacing loads of TTL with custom circuits.  The exact same evolution was occurring in the west with the PC environment, until nearly all the support circuits were integrated into just a couple large ASICs.   Its interesting to see the development paths of the Soviet computers and the West.  While they were entirely different instruction sets, they evolved in very much the same way.  East or West, LSI-11 or x86, at the end of the day, a computer is a computer and will evolve in similar fashion.

The Soviet-made 1801VM2 CPU (a binary-compatible implementation of the PDP11 instruction set and QBUS interface) was developed in 1982. The 1801VM2 is a further development of the earlier 1801VM1 doubling the original 5MHz clock speed. From a constructive standpoint this CPU is a completely independent development.

1801VM2 die – 1983 dated

1801VM2 Specifications

• Number of processor Instruction: 72
• Manufacturing process: 4 micron N-channel silicon gate MOS technology
• Die size 5.3 × 5.35 mm
• Transistor count: 18,500 active transistors, 120,000 integral elements
• Clock rate: Up to 10 MHz
• Performance: For register based operations (like addition) up to 1,000,000 instruction/s (1 MIPS) – for operations like multiplication, up to 100,000 instructions/s
• Supply voltage + 5V
• Power consumption: up to 1.7 W
• The case is 40-lead, ceramic DIP (KM1801VM2) or plastic DIP (KR1801VM2). (a surface mount version was also made)

To increase noise immunity in comparison with 1801VM1, additional ground contacts were made for the address / data bus.
The 1801VM2 was manufactured at two factories: Angstrem and Solnechnogorsk Electromechanical Plant (SEMZ).  As was typical of the time speed grading was done by adding extra marking to the chips post-testing.  Its very easy to miss these, if a chip was tested at 10MHz and passed it received no extra marking and was considered an 1801VM’A.’  If the device failed at 10MHz but ran at 8MHz a small dot was added to the package (and was considered a grade ‘B’ device).  This dot was not to be confused with the dot for the pin one marker, though often placed…next to it.

Ceramic DIP 1801VM2A Angstrem – 1989 No extra dot

Ceramic DIP 1801VM2B Angstrem – 1987 – Note the extra dot in this case by the date code

Plastic DIP 1801VM2A Angstrem – 1990

KN1801VM2- Angstrem 1985 CQFP Surface mount version (image Baator)

Ceramic DIP 1801VM2 Solnechnogorsk Electromechanical Plant – 1990 – Extra dot by pin 1 marker

In comparison with 1801VM1, expanded arithmetic instructions (MUL, DIV, ASH, ASHC – part of a the set of PDP-11 EIS), and also operations from the floating point instruction set (FIS) were added. The FIS instructions (FADD, FSUB, FMUL, FDIV) are realized through subroutines – when performing these instructions there is a special type of interrupt and the program handler in memory (“shadow” system ROM K1801RE2) of the console mode is executed, a ‘firmware’ style of FIS implementation, as its not truly hardware (the ROMs break down the FIS instructions into something the 1801VM2 can execute)
During the design of the microprocessor, a microcode error was made, leading to a malfunction of the processor when reading with addressing method 17 ( MOV (PC), R0).

DVK-1 Computer

The 1801VM2 was the heart of a number models of DVK computer. DVK was developed at the Research Institute of Precision Technology , Zelenograd (just outside of Moscow). The first model DVK-1 was developed in 1981, and released in 1983. Architecturally DVK copies mini-computers from DEC PDC-11 and PDP-11. By 1990, 200,000 DVK computers of the nine different models were produced.

Romashka Word Processor

Use of the processor continued well into the 1990’s. The “Romashka” belonged to the latest generation of electronic typewriters, which in their functionality were close to computer text editors. This typewriter made it possible to automatically format text (set alignment, change the spacing between characters and between lines, use bold and underlined fonts, etc.) and had an electronic memory of at least one page (3800 bytes).  In the West these half typewriter half computer were called Word Processors, and were quite popular through the 1980’s.   The machine’s control unit was a microcomputer based on the KM1801VM2 processor.
“Romashka” was produced by the Kursk PO “Schetmash” in the first half of the 1990s.

“Electronics IM-05 “- Soviet chess computer, contains 1801VM2 inside. It was a continuation of the line of chess computers “Electronics”. Produced by the Svetlana Association, Leningrad.

In 1984, the military-grade microprocessor 1806VM2 was released.
This microprocessor functionally corresponds to the 1801VM2, but is made using CMOS technology.

• Clock rate: up to 5 MHz
• Number of Instructions: 77
• Contains 134,636 integral elements
• Power consumption: up to 0.025W

The 1806VM2 developers fixed the microcode bug present in 1801VM2 (much to the relief, or annoyance of programmers). The 1806VM2 was supplied in a 42-lead dual in-line ceramic package with flat leads, N1806VM2 in a 64-lead CQFP. The rhombus marking on the chips denotes a military-grade device.

1806VM2 – Angstrem 1991 in the nice pink flat pack

N1806VM2 – Angstrem 1999 in a Ceramic quad flat pack

CQFP N1806BM2 on a ceramic substrate forming a military Single Board Computer – circa 1987 (image Baator)

These 1806VM2 are still being made by Angstrem, if you need to build a PDP-11 computer to run Tetris on, or repair a Buran shuttle you may have laying around.

In 1990, a radiation-hardened microprocessor was introduced, compatible with the 1806VM2, known as the 1836VM2/N1836VM2.  Just like in other countries, existing code base and known reliability are more of a driver of what the military/industry uses than having the latest and greatest.  There are still MIL-STD-1750A processors being made and used, rad-hard 8051s and 80186s, and Soviet PDP-11 processors right there with them.

Photos of microprocessors from the collection of Perfiliev Andrey (Andreycpu).
Article written originally by Contributing Author Vladimir Yakovlev (edited by cpushack)