TCS008 Adder – TCS017 FPU Control and TCS060 Shift Register – 1974-1975

Today most chips we use are made in CMOS (Complimentary Symmetrical Metal Oxide Semiconductor), which is a process using both p-type and n-type MOSFET transistors.  It was invented back in 1963 by Fairchild, but was commercialized by RCA in 1968 with the introduction of the CMOS based 4000 series of MSI logic devices.  These were basic IC’s with such things as NOR gates, Adders, Flip flops and the like.  A CMOS equivalent to TI’s popular TTL based 7400 series.

RCA also made a series of computers in the 1960’s (to compete with IBM) as well as other electronic products. including many for the US Air Force, NASA and US Army.  In 1970 RCA created the SSTC (Solid State Technology Division) in Somerville, New Jersey to develop CMOS processes (and Silicon on Sapphire versions) into more commercial products. At the time most IC’s (outside the 4000 series) were made in PMOS or NMOS, CMOS was considered too slow, despite is lower static power usage and high noise immunity.  SSTC was to develop processes, standard, and eventually devices, that RCA could then commercialize and/or use in their other products (such as their computer line, radios, and military products).  It was out of this project that the famous COSMAC processors (CDP1801 and CDP1802 line) came from.

TCS002 16×16 Multiplier 200ns – Note the hand written characterization markings – 670uA @ 5V

SSTC also made a series of essentially standard test devices.  These were based on a common cell architecture (more common in ASICs today) with a series of chips made to demo what was possible with the CMOS-SOS (CMOS on Sapphire) process.  These ‘standard’ IC’s would then be used in various demo products for potential customers.  The most interested customers at the time were the US Air Force and NASA.  The RCA CMOS process allowed for a great power savings, and especially when built on a sapphire substrate, exhibited a high tolerance to radiation, useful for the then rapidly expanding satellite/space market.

AN/GVS-5 Laser Range Finder – 1970’s. They were huge, but very impressive for their day

The first of these chips were made in 1974-1975 and were made with a 7 mil (178micron) standard cell height, on a 20 micron process.  Versions were also made with a 5 mil (127 micron) size, specifically for the military market.   These were not typically commercially available devices, but used internally for test, evaluation, and to build specific products, though the technology used for them was often turned into generic products.

Below is a list of some of these devices SSTC made. The TCS prefix was used to denote these being made by SSC on a CMOS-SOS process.  A TCC prefix is a standard CMOS process.

**Used to build the NASA 32-bit SUMC (Space Ultrareliable Modular Computer)

These were used in many military products such as the AN/GVS-5 handheld laser rangefinder, a Programmable waveform generator used in FM RADARs, and for the imaging system (digitization and compression of video to be sent) in the remotely piloted Lockheed MQM-105 Aquila drone (yah drones, back in 1975).  The Aquila project was particularly challenging, as the circuitry had to be small enough, and low power enough to fit on a small airframe, yet still handle video compression fast enough that a ground station could receive and decode useful imagery.   This was done with several large hybrid circuit modules consisting of many TCS057 Multipliers and TCS065 Adders.  This was capable of 200-1600Kbps data rates, not bad in 1975.

Aquila Artillery Spotting Drone (Lockheed Martin)

Most of the TCS line of components was capable of 10MHz operation while running at 5V, and voltage and clock rate scaled with each other, so they could be clocked lower for less voltage and power usage, or clocked higher at the expense of more power.

It is a bit unfortunately that RCA lost its way in the 1970’s, attempting to became a conglomerate, they became known as Rugs, Chickens and Automobiles (having bought parts of Hertz Rental Cars, a frozen TV dinner company, a carpet company and others).  They were bought by GE in the 1980’s and in 1988 the Solid State Division, with what remained of the SSTC was purchased by Harris Corporation, which continued to make the 180x line of CMOS processors for over 20 years.  If RCA had stayed focused on making CMOS a commercial success, we may have had more and faster CMOS processors nearly a decade sooner.

NEC uPD70108C – V20 CPU – Late 1984

NEC had a cross license agreement with Intel dating back to April of 1976 that allowed each company to make/sell products based on each others patents.  This was particularly important in the 1970’s as having a viable ‘second source’ for your designs was considered critical for it to be viable in the market.  This was especially true for Intel, who wanted to get into the Japanese market. In 1979 NEC began to produce and sell the 8086 and 8088 processors.  NEC wasn’t going to succeed by just being a second source to Intel though, designing their own processors was of great importance.  While producing the 8086/8088 they also began working on their own version, which would be an enhanced 8086/8088 processor.

NEC V30 Die (courtesy Birdman) – 8086 with many enhancements

The result was the rather well known V20/V30 processors of 1984.  These were not just clones of the Intel MCS-86 (though determining this took several court cases and resulted in the Chip Act of 1984).  The V30 had some pretty big differences, notably, internally it had dual 16-bit busses, allowed data to be moved much more efficiently, as data could be moved into and out of a register at the same time (nearly).  It also increased the microinstruction word from 21 bits to 29 bits, added a hardware effective address generator, additional instruction pointers, and a hardware shift/loop counter.  Taking advantage of these features added some new instructions as well, 156 compared to the 8086’s base 133.  The V30/V20 were the beginning of a line of V-series processors.  NEC went on to make  ‘186/188 style processor (the V40/V50) as well as a series of microcontroller versions  (V25/V35 and others).  The V20/V30 were to be supported by a math coprocessor like the 8087 called the upd72091.  Very little info is available on the 72091 as it was cancelled very early on in its design, as by 1984-1985 it was already out of date.  Its replacement was to be a bit more powerful.

Design of the the upd72191 started likely at the same time the V30 was released, around 1984-85, with specifications released in 1986, and plans for chips by 1987.  This chip was in an advanced state of planning, such that many products, including motherboards (such as the Ampro Little Board PC) and industrial controllers designed with sockets for it.  Preliminary datasheets exist, but alas, no chips seem to be found.

LittleBoard PC (Ampro) with support for canceled upD72191 (V40 based)

The upd72191 was made in CMOS and is a bit like an enhanced 80C187 but with support for the V20/V30.  It is fully IEEE-754 compatible (the 8087 wasn’t as the standard wasn’t finished yet) and supports a similar instruction set as the 80C187 (and thus the 80387).  Unlike the 8087 it supports the full set of Exponential, Trig, Logarithmic, and Hyperbolic instructions.  The 8087 was somewhat limited in this, as it was already pushing the limits of what was possible on a single chip at thee time of its release.  The 72191 supports FSIN/FCOS which the 8087 doesn’t and many other functions (its full instruction set could not be found).  The 72191 has a mode pin that selects between interfacing between the V20/V30 and the V40/V50, (as these talked to coprocessors differently) so it was compatible with 4 distinct processors.  The 80C187 could only be used with the 80186 and the 8087 could only be used with the 8086/8088.

upD72191 FPU Block Diagram – 1986ish

Looking at the block diagram of the ‘191 we notice something else, its a dual bus design, much like the V30 processor.  Internally there are a pair of 74-bit busses for the mantissa (fraction) side and a pair of 16-bit busses for the exponent side.  This is a striking difference from that of the 8087 and the ‘187.  The 8087 has a single 16-bit bus for the exponent, and a 64-bit (68-bits into the shifter and ALU) for the mantissa.  There are 3 extra bits for enhanced accuracy, and a extra leading bit that is always 1 for floating point math, giving 64 bits of ‘data’.

The dual bus design makes sense as NEC did the same for the V-series.  Coupled with the right microcode, it can greatly enhance the speed of the FPU.   So why then is the bus expanded to 74-bits for the mantissa?   In the 80187 and 80387 this bus is still only 68-bits.  We look to the design of NECs follow on FPU for the answer.  The upd72291 (and its 32-bit bus 72691 version) are rather different beasts, made for the the V33/V53 x86 CPUs and V60/V70/V80 non x86-CPUs.  We’ll talk about them in more detail later, but they share the same 74-bit mantissa as the 72191, and in this case, the designers wrote a paper on its design.

The FPP [72691] is the only floating point processor that provides the power function x^y.  This function (called FPOWER in the instruction set) is difficult to implement not only for its complex definition but also for sufficient accuracy. The equation X^y = e^(y*log_eX)
does not give good accuracy because the accuracy error of the log function is augmented by the exponential function.  The FPP solves this problem by providing a 74-bit data width for the mantissa data bus.

Being as the 72191 was canceled, the ‘291/691 would in fact have been the only FPU to support this in hardware, but it seems it was first implemented on the ‘191.  The solution only works well for larger (greater then 32) values of y, otherwise iterative multiplication is used, but where it can be used it greatly speeds up the calculation.

When the 72191 was canceled NEC thoughtfully provided a single chip solution called the upd9335C for allowing an 8087 to be interfaced to the V40/V50 processors which, like a 186, used a HOLD/HOLDACK bus release protocol instead of the 8086/8088s (and V20/V30s) REQUEST/GRANT.  For applications using a V20/V30, an 8087 could be used directly.

NEC upD70632R-20 20MHz V70 Processor

In 1989 NEC released the next of the V-series, the V60, V70 and later the V80 processors.  These were a departure from the previous in that they were no longer based on the x86 architecture, but rather a completely new ISA (though the V60 and V70 had a V20/V30 emulation mode).  These were full 32-bit designs, and were Japan’s first widely available 32-bit processors.  Of course with a new processor comes the need for a new FPU and NEC had not one, but 2 FPU options for these.  The upd72291 and upd72691 are based on the same design, but with some major feature differences.  The 72291 is designed to work with processors that have a 16-bit data bus such as the V60.  It also could be used with the older V33/V53 x86 designs.  Internally it has eight floating point registers and supports all your typical floating point functions as well as vector math functions.  The upd72691 is designed for 32-bit data paths, but adds a bit more…

NEC updD72291R-16 FPU

In addition to expanding the register set to 32 FP registers, the ‘691 also added a complete suite of matrix  math functions. The ‘691 was made on a 1.2u CMOS process and contained 433,000 transistors. (nearly 50,000 MORE then the V60 processor) Running at 20MHz it was capable of around 6.7MFLOP and supported 24 vector/matric instructions as well as 22 mathematical functions.  Like the 72191 it had a 74-bit mantissa datapath, but expanded the exponent path to 17-bits to support double extended precision number formats. It is a highly microcoded design using a 3072 word (43 bit word) microcode ROM, 20% for vector/matrix, 37% for arithmetic, and the rest for exceptions handling and other house keeping instructions. Interestingly, these microps themselves encode additional instructions that NEC call nano-ops, these controlled just the ALU operations of the instruction (the rest being bus control and sequencing).  These nano-ops were stored in a 256 word x 74-bit Nano ROM (only 120 words were used, the rest for potential expansion). This was the last of the line of NECs dedicated FPUs (excluding the few MIPS FPUs they made).  Its a bit ironic that it seems they canceled as many designs as they made.

…but perhaps they didn’t?

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Introduction

On this site you can read about thousands of processors models. And every year it is more and more difficult to write about some new (old) processors, since everything has been known for a long time. But there are also exceptions to the rule which we love to find. In 2021, I learned about one unusual processor, the information about which I want to share with you. The roots of this processor’s history go back to Italy, in the distant year or 1998. This time just falls on the confrontation between Intel and its second generation Pentium and AMD K6-2 and K6-3 processors. The Cyrix MII processors from Cyrix Corporation, IDT WinChip 2s and Rise mP6s were still going strong as well.

But before we talk about the Genesys B52 MMX processor, we should take a closer look at Intel Pentium II processors in general, as the Italian processor primarily owes its appearance to them.

Intel Pentium II

From 1993 to 1997, the Pentium dominated all market segments. Over time, the name of the “Pentium” trademark even grew into a household name (Its all about the Pentiums baby), but with the release of the Pentium II, everything changed. If earlier Intel did not deeply segment the market, there were Pentium Pros for workstations and servers, and for everything else there were various models of Intel Pentium processors, in which, at the end of their domination, Intel added MMX instructions, depriving and thereby putting an end to its server segment. The new slot form factor of the processor, the abandonment of the usual pins and ceramics and further segmentation of the market (using Intel Celeron processors and the new Xeon line) radically changed the further course of development of the history of microprocessors.

May 7, 1997 saw the light of the first models of Intel Pentium II processors, manufactured on a 350nm process with a core voltage of 2.8 volts. The first models were based on the Klamath core (named after the river by which The CPU Shack is located) core, operating at 233 and 266 MHz. The main differences from the Pentium Pro predecessor it was based on were the L1 cache increased from 16 to 32 Kb, and the presence of a block of SIMD instructions called MMX first introduced on the last P55C processors. Like the Pentium Pro it featured its own L2 cache on the module, but in this case it was 512KB fixed on the same PCB as the processor core, a much cheaper solution then the dual ceramic cavity package of the Pentium Pro.

Before the Pentium II, only the Pentium Pro could boast of its own cache, running at the frequency of the CPU core. But, placing the CPU core and L2 cache on the same substrate was an expensive pleasure even for Intel, and the processors had to be cheaper for better competition, which was getting more and more intense. Intel then made a “wise” decision, as a result of which the Pentium II got a its own L2 cache next to the CPU core This engineering solution significantly reduced the cost of manufacturing processors. BSRAM L2 cache chips were manufactured by Toshiba, SEC and NEC at that time, rather then being made in house by Intel, further easing the cost burdens.

Pentium II Klamath SECC1 PBGA Core 2 x Cache on front 2x + TAG on back

For all models of Pentium II processors, the cache size remained unchanged and equaled 512 KB, while different Pentium Pro models had a cache from 256 to 1024 KB. The L2 cache of the first Pentium II processors consisted of four microcircuits located on both sides of the cartridge processor board and operated at half the core frequency. In addition to the processor core and 4 L2 cache chips, there was also a tag-RAM chip on the cartridge PCB, a total of 6 IC’s.

Backside with 2x cache + TAG

The tag-RAM size/configuration determines which range of main memory can be cached. For example, if the L2 cache is 256 KB and the tag RAM is 8 bits wide, then this is enough to cache up to 64 MB of main RAM. However, if you add additional RAM in the process, it will not be cached unless you also expand the tag RAM. On Socket 1-3 486 systems, most motherboards allowed adding and modifying additional L2 cache and tag-RAM chips for this purpose. The Pentium Pro had built-in L2 cache and tags capable of caching up to 4GB of main memory, whereas the first Pentium IIs could cache up to 512MB of RAM.  This was in part to set them apart from the server oriented Pentium II Xeon which had full speed cache capable of caching 4GB (or 64GB with PSE-36),

In January 1998, Intel announced the Pentium II processor, built on a new core, codenamed Deschutes (Another river in Oregon). The processor core was manufactured using the smaller 250nm process, which lowered the operating voltage to 2.0 V, instead of 2.8 V for “Klamath”. The L2 cache of 512 KB still worked at half the core frequency, but it was made in the form of two BSRAM chips located to the side of the processor package. In later modifications of the Pentium II Deschutes core, Intel replaced the tag-RAM chip, thanks to which the processors could cache up to 4 GB of RAM (the 82459AD revision).

The first generation of Intel Celeron processors were based on the “Covington” core were essentially processors on the “Deschutes” core, but without ANY L2 cache. Thanks to this, they had very poor performance, but they overclocked very well, demonstrating the best overclocking figures up to double the nominal clock frequency.

Deschutes core with Organic BGA core and 2x cache chips on front. TAG on back

All overclocking of Pentium II, as a rule, rested on the characteristics of microcircuits used by BSRAM and tag-RAMs. The latter, like the cache, was much disliked voltage rises, and with inept handling, an expensive Pentium II could turn out to be a Celeron “Covington”, if such microcircuits failed.By the way, they warmed up decently on Pentium II processors based on the “Klamath” core so cooling was very important as well. The multiplier in 99% of Pentium II processors was locked (very early production ones were unlocked and Engineering Samples of course), so overclocking was performed by raising the FSB frequency, this being dependent always on the cache and TAG chips installed in that particular processor.

A simple example. In Costa Rica, where Intel has an advanced advanced processor assembly/test factory, which simultaneously assembled high-frequency models with 450 and 300 megahertz. The cartridge and core for these processors are identical (and the multiplier was the same 4.5x as well 66×4.5 for the 300 and 100×4.5 for the 450). The difference was only in the installed cache memory with different speed rating in nanoseconds. Sometimes on the assembly line there was only a fast cache memory capable of operating at a frequency of 225 MHz, intended for models of processors with 450 MHz. In this case, it was also installed on the model with a frequency of 300 MHz, as a result of which they overclocked perfectly.

Genesys B52 MMX CPU

The history of the Italian processor began in the city of Monopoli, in the province of Bari in Italy. In 1998, Italian Marcello Console founded Genesys, which initially employed 10 people. The main idea of the Genesys business was the production of modified Intel Pentium II processors based on the “Deschutes” core, at a much lower price than the Pentium II ones of similar clock speed. Plus a warranty period extended to 3 years and productivity increased by 5% or more. It turns out to be a solid Attraction of Generosity!

Genesys had registered its own domain www.b52mmx.com and is getting ready to implement their processors in ready-made system units. Unfortunately, nothing is known about the manufacturing process, it remains a mystery to this day. There is not so much information on these processors, but let’s try to figure out what these processors were.

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Semiconductor Complex LTD SCL6502 CPU

India in the 1970’s was often considered a third world county, supported by a largely agrarian economy and with a wide swath of the population still based off of subsistence living.  They also however, had a robust space program, had mastered nuclear technology and had a largely stable government that supported the advancement of technology development in the country.  All the pieces were there to begin making the shift to the robust high tech economy that they possess today.  In the 1970’s India had several govt entities working on semiconductors and electronics, all managed under the direction of the Dept of Electronics.  There was also a fair number of companies with plants in India doing electronics manufacturer and assembly.  This was largely small scale production of older technology.  TTL circuits  (starting with the 7420) were made in Bangalore by BEL back in 1971.  But TTL circuits won’t get you far, and at that time the best process India had was around 8 microns, so in 1972 an initiative was started to develop an indigenous semiconductor industry within India.

SCL Fab – Currently 0.18 Micron

Politics are the same everywhere, and so this process took some time, people with experience had to be recruited to run it, and a suitable (politically and geographically) location selected.  Eventually in the late 1970’s the Semiconductor Complex LTD was formed in the city of Mohali ( Chandigarh ) in the Punjab province of India.  SCL was to be the state supported enterprise to bring indigenous high end (LSI and above) semiconductor production to India.  Two things were needed to make this work: Technology, and People who were experts in that field.  SCL was tasked with going to Japan, America, and Western Europe in search of a company that would assist with the technology transfer, as well as finding some Non-Resident Indians who would be willing to come back to India to work on it.  Many Indians had high skill jobs in the industry outside of India, and it turned out convincing them to come back to help their country was a non-issue (though generous incentives were provided).  Getting the technology on the other hand was a bit more work.

The first trip of the technology transfer team of SCL was to Hitachi in Japan.  Negotiations with Hitachi were grueling, and while not unproductive, did not yield the results SCL wanted.  Hitachi was happy to license some designs to SCL, for a high fee and royalties, but did not want to immediately help create the 3-5 micron production fab that SCL envisioned.  Hitachi called thei ‘one step at a time’  whereas the Indians wanted to go all in from the start.  Hitachi agreed only to help (some) with a 5 micon process) and only to license products for digital clocks and watches.  The SCL team then turned to the United States, likely expecting similar results.

The chosen company in the USA was AMI (American Microsystems Inc), a company with 7-8 times the turnover of Hitachi.  AMI was at the time the largest maker of custom ICs in America, as well as a very large provider of second source ICs  (such as the 6800 and 9900 CPUs).  AMI’s CEO Roy Turner readily agreed to help SCL, much to the surprise of their negotiation team, and on the very first day offered SCL AMI’s 5 micro CMOS and NMOS processes, with the option to license their 3 micron CMOS and NMOS processes within 4 years of the agreement becoming effective.  AMI also offered SCL access to all of AMI’s standard products catalog, as well as the possibility of joint development of additional products, all at a simple 50/50 split.  AMI even offered to help with the technology export license that would be required by the US State Dept to transfer the fab tech to India.  The agreement was signed in April of 1981.

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Intel Pentium P54CM – Q0475 Engineering Sample from November 1993

Today dual processors are incredibly common, even in home computing, and multicore processors even more common, but there was a time when this was not so.  There were of course multi-processor systems in the 80’s and early 90’s, but these required extensive additional hardware to support them.   Three main concerns for design multiprocessing systems are how to efficiently handle interrupts (which CPU handles what), how to ensure the caches are kept current (and not used if they aren’t), and how do processors share the same bus.

Bus sharing was largely handled already as busses have long been shared by all sorts of devices.  Interrupts were made easier by the release of the APIC (Advanced Programmable Interrupt Controller) standard by Intel in the early 1990’s.. The first version of this was implementing in the 82489DX IC.  Each CPU (486 or original P60/66) would need its own 82489DX (Local APIC) and then yet another one to work as an I/O APIC.  Clunky, but it worked.  The BIOS and OS were designed to help with cache coherency coupled with the a modified MESI protocols in the processors themselves for keeping track of what cache items were valid or not.

P54CM50-75 Q033 – Early October 1993 Sample – 75MHz modified Socket 5

After the release of the first (P5 Socket 4) Pentiums Intel decided to integrate  an APIC onto the CPU core itself.  This greatly simplified dual processor setups.  Within only a few months of the release of Socket 4, Intel was already working on the P54C Pentium.  These were to be on a whole new socket, Socket 5 (much to the annoyance to those who had just dropped some serious coin on a Socket 4 system).  The Socket 5 systems, using the Intel Neptune 430NX chipset, would support dual processor systems.  To do this Intel designed a separate Pentium Processor core called the P54CM, and originally, a separate, slightly modified socket for it.  The secondary socket had a slightly different pin out, and was to run the P54CM processor, OR, could be used as an OverDrive socket, with the Overdrive becoming a second CPU (why both, no one is entirely sure).

P54CM50-75 Q033 – Mod Socket 5 – Oct 1993	Q0475 Nov 1993 – Standard Socket 5

Samples of the P54CM debuted in October of 1993 using the new pinout.  Samples from just weeks later had reverted to the standard Socket 5 pinout, clearly someone at Intel decided that yet another socket (and package) design would be uneconomical.  The separate core, however, remained.

Early Pentium Print Ad shows the modified Socket.

The P54CM core was only produced in a very few specs, SX874 B1 stepping in STD Voltage (3.135V–3.465V) and the SX942 (STD) SX943 (VRE 3.3V–3.465V)  and SX944 (MD: faster timings on several pins/3.135V–3.465V) series in the B3 stepping.  There were also several ES versions made: Q033 P54CM50-75, Q0475, Q0519 and Q0520 with the B0 stepping and Q0543 with the B1 stepping.  These processors, including the production versions, were incredibly rare.  Very few companies used them in actual machines.  Why? Because a normal (providing it supported dual processing) P55C could be ran just as well.  The only real difference in the P54CM core was the DPEN/ output pin was driven low on RESET.  On a P54CM this pin is an output that tells the primary processor ‘hey a second processor exists’ while on the standard P54C, DPEN/ is an input.

SX874 – P54CM-B1 (with the FDIV bug) from October 1994

It turns out that the P54C/CM core ALSO has a CPUTYPE pin that can be be set to tell a system that the processor is a secondary processor or a primary (and early Pentium Dual boards had a jumper to do just this.)  You didn’t actually NEED a P54CM as the secondary processor. a normal P54C would work just fine.  There was even some trickery to allow a system to boot off of a secondary P54CM CPU, not officially supported by Intel, but in systems designed for redundancy, the DPEN/ pin could be overridden and the P54CM used to boot a system (normally the primary CPU would handle all the boot up duties and only enable the secondary CPU once it was ready).

Later Socket 5/7 Pentiums (C0 and later steppings) supported multiprocessing natively with a few exceptions.  The SU114/SL25H Pentium 200s did not have a functional APIC so thus were not DP compatible.  These were even mismarked by Intel, with the marking ‘VSS’ on the back.  That last ‘S’ means they were tested to support UP, DP and MP configurations, when in fact they were not, the code on the back should have been VSU (‘U’ means they were tested for MP, and uniprocessor, but NOT DP, as DP required a working APIC).  The SY045 (200) and SY037 (166) were also ‘VSU’ processors, not tested for DP use, likely because of some issue with the APIC.

Mismarked SU114 (VSS) and correctly marked SY045 VSU

Intel Overdrive processors suffer a similar fate, they will not run in the primary socket of a DP system, but will in the secondary socket.  This is mostly likely because the DPEN/ is not supported as an input on the Overdrive, so it wouldn’t know a secondary processor exists, a shame really as a dual OverDrive system would be pretty neat.

At he beginning of the P5 era Intel seemed to be all in on DP systems, but with the coming release of the Pentium Pro, they began to use Dual Processing as a way to differentiate their products.  DP support was removed in the next Pentium chipset (the FX Triton) only to later return in the HX Triton II.  The VX and TX Pentium Chipsets also lacked DP support.

Quite famously later in the 1990s Intel marketed the Pentium II/III with multi-processor support, and sold the Celeron as uniprocessor only.  It turned out that the lowly Celeron was quite happy to run in DP configuration, much to the annoyance of Intel, but joy of enthusiasts around the world.  Perhaps someone will figure out a way to run Pentium Overdrives in dual processor systems, if there is a will there tends to eventually be a way.

National Semi NS486SXF-25 Rev C0 -1999

While I was casually reading an issue of ‘Boot’ Magazine from 1997 I was sent down the rabbit hole by a mention of a processor in a small blurb in a footnote of an article.  Just a few lines really is all, but about a processor I was not familiar with, an x86 one at that! So nearly a month later, I have emerged from the rabbit hole.  We will begin not with what sent me to the hole in the first place, but when and where the hole itself came from, and that is the year 1995, the place? National Semiconductor.

As mentioned in the 486 Overclocking article, the 1990’s were a boon for up and coming x86 processors.  In some ways it was similar to the processor bonanza of the 1970’s but centered on x86.  Many companies wanted to have a go at the x86 architecture market.  National Semiconductor was of course interested in making something with x86 as well.  They rightly decided that a head to head competition with Intel for mainstream PC processors wasn’t the best idea, but that embedded computing, low cost set top box (as they later would become) and ‘Network PC’s’ would be a good market.  The goal was to design a simple efficient x86 processor and integrate it with many peripherals, and sell it for $20-30 each.

Elentari Core. 16-byte Prefetch Buffer, 1K Cache ,16-bit Data Bus and support for 2 8M DRAM Pages

NS486SXF/L Block Diagram (SXL omits blocks in dashed lines)

The core project began in very early 1995 (or late 1994) and was known as the Elantari, Queen of the Stars in Lord of the Rings Mythology.  The Elantari (aka the ESF94001) had three priorities in its development (in order): 1) Schedule, 2) Low Cost, 3) Performance.  Time to market was essential, even at the expense of performance optimization. The core (which the Marketing dept quickly renamed to the NS486) was to be a 486 compatible core (using protected mode only) with some optimizations and was organized officially under a new unit at National Semiconductor called the Arador Unit (someone really liked LotR). Target speed was 25MHz at 5V on Nationals 0.65u process using a very simple 3-stage pipeline (Fetch/Decode, Execute, Write Back).

NS486SXL-25 No Rev Marked 1996 (courtesy xSecret)

Balancing cost and performance meant that die area should be minimized, as this effects yields and parts per wafer.  This, on a 0.65u process, allowed for a small area of cache.  National ended up, after a fair amount of analysis, going with a 1K direct mapped instruction cache (that can bus snoop) and a 16 byte prefetch buffer.  This is in great contrast to the Intel 486 which had a 8KB unified cache (and 16K on later 486s).  But for embedded use instructions have a better performance increase when cached then data.  Cache also presents some difficulties with real time computing, as its difficult to know how long an operation will take if you don’t also know whether it s from cache or the main memory.  National provided a method on the NS486 to load and lock the cache with a set of instructions that would ALWAYS operate out of cache.  This combined with assigning one DRAM page to Data, and another for stack use, made timing more predictable and consistent when needed.  As part of the development process National used IP they had licensed from another IIT, whom had earlier designed a 486 class processor. IITs IP was not used in the NS486 itself, but was used in helping debug, design and develop it and its testing environment.

NS486SXL-25 Rev A – SXL unique die – 1998

The NS486 core lacked both a FPU and MMU, and had a 16-bit data bus.  This allowed for a fairly small core size.  The core alone took up about 256,000 transistors (roughly half of what the Intel 486 integer core used) and on the initial 0.65u 3-layer process results in a core die size of 29.6mm² including the cache. (the SXL die with limited peripherals pushed that to around 64mm²)  The short pipeline greatly restricts the speed, it never made it above 25MHz (though 33MHz was apparently achievable.

National Semiconductor by this time had become dominate in integrated peripheral chips, led by its ‘SuperIO’ chip line, and it was this integration that made the NS486 unique.  National designed two versions of the NS486, the NS486SXF with a full set of peripherals, and the smaller NS486SXL with a few less.  The integration of peripherals was one of the most challenging aspects, the core itself is relatively simple, but adding other features, often with different clock and signal domains is much harder to design and test.  This is where National’s expertise on SuperIO chips came in handy.

The other challenging aspect of a x86 design in the 1990’s was from the legal department.  Intel claimed that even a clean design of anything x86 ‘MUST’ violate at least one Intel patent.  National however had designed the NS486 from the ground up, including the microcode, AND as a backup, also possessed a license from Intel dating back to the 1970’s (it was that license that helped lead to the National/Cyrix merger).

	NS486SXF	NS486SXL
Package	160PQFP	132PQFP
Cost	$25	$15
486 Core	X	X
DRAM Controller	X	X
DMA Controller	X
LCD Controller	X
ISA Bus Interface	X	X
External Bus Master Controller		X
UART/IrDA	X	X
ECP Parallel Port	X
PCMCIA Controller	X
Real-Time Clock, Timers	X	X
Programmable Interrupt	X	X
Reconfigurable I/O	X	X
Programmable Chip Select	X	X
3-Wire Serial Peripheral	X	X

NS486SXL Rev A0 die – matches package markings – Still 0.65u (courtesy aberco)

Initially both the NS486SXL and SXF used the same die, with the SXL having some of the onchip features disabled. National planned on making a seperate die later for the SXL to further reduce costs.  They did this in around 1998.  Their goal was also to shrink the design to their upcoming 0.35u process but it is unknown if they successfully did this (dies from 1998 continue to be of the 0.65u variety).

Initial samples were available by early 1996, a rather quick development.  The NS486 was well supported in both hardware and software.  It supported a number of common real-time operating systems of the time, including pSOS+, QNX, VxWorks, and VRTX. It did not however support DOS, having no real mode support. In 1997 the NS486SXF was used to implement Jav Nanokernel, a Java based OS running the Java VM directly on hardware. Hardware vendors included PARVUS (NS486 based PC104 board), BCT (Dev Boards) and several others making ready made NS486 based SBCs.   In November of 1996 National released a full Web Browser based Network computer Reference design using the NS486 called the ‘Odin’  This was the first sub-$200 web browser capable computer of the time.

NS486SXL die – Peripherals take up about a third of the die (die photo from aberco)

In 1997 things got a bit more interesting.  National Semiconductor decided to merge (in all reality it was an acquisition) with Cyrix.  The NS486 continued to be made, but by 1999 National listed it as ‘not recommended for new designs’  It would also appear that some things never really got finished.  Datasheets up through at least Dec of 1997 were still ‘Preliminary’ though the silicon had been produced for sometime.  Production of the NS486 continued well into the 2000s, with chips being made at least into 2003 and probably later.

The NS486 Performance in integer tasks was pretty good. In some cases beating the Intel 486DX. THis is largely because of its optimized instruction timing, many are single cycle, much faster then other cores.

At the time of its introduction it had little competition (in the x86 realm).  Intel had the 386EX and AMD had an the 386SC (what later became the ElanSC300 line).  Both of these were 386 class parts that were slower (and in the case of the 386EX) more expensive.  Intel themselves did not have a good embedded 486 option largely due to lack of trailing edge fab capacity.  Most of their fabs had been (or were being) converted to higher end processes to make new Pentiums and P6 chips, while their older fabs were filled to the brim with Intel’s then booming chipset business.

*Estimated Core = 256k Cache = ~50k

It was suggested that if National lengthened the pipeline of the NS486 to the then standard 5-stages, and moved it to their new 0.35u process that it could ‘easily’ hit 133MHz at 3.3V.  But what embedded designer would want to have to deal with that fast of a processor?  It would seem that the NS486 team had ideas beyond just the purely embedded market, as something more then the NS486 was their ultimate goal, and exactly what led me down this Rabbit hole……

In Part 2 we’ll look at what National developed from the NS486, and if it wasn’t for the MediaGX they acquired, very likely would have made it to market.

Before beginning the history of the Soviet 580 series microprocessor, we need to say a little bit about the level of Soviet computing technology before the advent of integrated microprocessors. This is really a topic for a separate article, so just two facts.

This article is largely from guest author Vladimir Yakovlev, translated from Russian, and edited/expanded by me.  It is part of a series on Soviet microprocessors that started with the Soviet T34 Z80 article. 

In 1950 the “Small Electronic Computing Machine” (SECM) was made in the USSR. It should be noted that in the USSR this computer was launched at a time when there was only a few computers in Europe, the English EDSAK, launched just a year earlier and Zuse’s Z4 in Zurich in ~1947. But the processor of SECM was much more powerful by parallelizing the computational process.

In the creation of the SECM, all fundamental principles of computer creation were used, such as the presence of input and output devices, the encoding and storage of the program in memory, the automatic execution of the computation based on the stored program, etc. Most importantly, it was a computer based on binary logic used and currently used in computational engineering (the American ENIAC used a decimal system (!!!)).

In 1975, during the historic Soyuz-Apollo space mission, the control was carried out by the complex, which included the BECM-6 (Big Electronic Computing Machine), a direct descendant of SECM. This system allowed for one minute of flight computation time, while on the American side of the flight it took 30 minutes of computation.

BECM-6 (Science Museum, London)

The real tragedy was the decision to produce IBM-360 clones in the USSR, that is, the transition to copying American architecture. I mean, obviously, whoever’s copying doesn’t have a chance to outrun (THe the USSR regularly added enhancements to Western designs). Copying has only one meaning – as a stage of learning. When you don’t have your own technology. Today, China is demonstrating the effectiveness of this approach. But the logical end of such an approach is still a shift to proprietary developments.

From that moment on, the Soviet Union was catching up.

At the end of 1962, by the decision of the Government of the USSR, the Kiev Design Bureau was established in Kiev, later the Kiev Institute of Microdevices (KNIIMP), with an experienced plant. It was KNIIMP that was chosen to copy Intel’s products. The first task was to create a copy of the i8080 and was started in August 1976, just 2 years after Intel introduced the 8080 to the Western World.

In 1977-1978, the first prototype chips were completed. The first basic set of the series contained three chips, K580IK80 (8080 CPU), K580IK51 (8251 USART) and K580IK55 (8255 PIO Controller).

They were produced in 48-lead metal-ceramic planar package. Contrary to popular belief, it is not a layer-by-layer copy of the Intel 8080 (some blocks are similar, but the layout and location of the bonding pads are significantly different). On November 6, 1980, the New York Times published an article “Soviet Gaining in Computers”.  in which the author of article also reached this conclusion.  These ran at 2MHz (500,000 ops/ec) and were made on a 6 micron NMOS process.

In 1981-1982 the package were replaced with the standard (Soviet pin spacing) DIP. Both versions for the domestic economy in plastic cases and for special applications in metal ceramics were released.

580VM80 – 1988 – Military spec

Around 1983, the names were changed from IK80 to VM80, IK55 and IK51 to VV55 and VV51 respectively. The additional letter “A” denotes an upgraded version of the processor from the extended base set of the series. In this variant, the speed was increased to 2.5MHz 625,000 op/s, the area of the die was reduced by 20%, (resulting from a process shrink to 5 microns) and the periphery of the crystal was redesigned.

KR580IK80A – 2.5MHz – 1982 – “KWAZAR” (KIEV, UKRAINE)

The 580 series was produced by many of the Soviet IC design houses, for many years.  Including, Kvazar, Electronpribor, Rodon, Kvator and Dnepr.

KR580IK80A “ELECTRONPRIBOR” (FRYAZINO, RUSSIA)
( “O” – pre-production sample)

“KVANTOR” (ZBARAGH, UKRAINE)

“RODON” (IVANO-FRANKIVSK, UKRAINE)
Top package is a early (1983) ‘Chocolate’ Brown PDIP

Late Production (1991) KR580VM80A – “DNEPR” (KHERSON, UKRAINE)

Chips manufactured for export were marked with the inscription Сделано в СССР and didn’t have the logo of the manufacturer.  The ‘manufacturer’ was the USSR, as that was more important then which state enterprise it came from, as a matter of national pride.

Export version (for Export to other Soviet Aligned countries)

In a sense, reproduction of microcircuit analogues is akin to a very high quality translation of foreign literature into native language. It is necessary not only to completely transfer the purpose of the product itself, but also to make it technologically compatible for the domestic producer. This is a very difficult task.

While the 8080 and 8086 microprocessors were at issue, the KNIIMP was successfully performing its task. But once Intel developed and started the 80286 and then the 80386, the Soviet Union was unable to produce similar microprocessors.

It can be argued that Intel Vice President Robert Noyce’s suggestion has been fully realized – the Soviet Union had fallen behind the United States in the development and production of modern microprocessor circuits forever.  Even to this day Russia continues to make variants of Western processors, from the MCS-96 series, to Microchip PIC17’s.  It should be noted that they did make a myriad of somewhat custom microcontrollers for specific tasks, that did not have direct Western Analogs (though sometimes they claimed these devices to be analogs of chips that they were not, in order to meet the direction of ‘copy the West’)

Before we get into the fascinating story of the Soviet (specifically the Angstrem) Z80 clone it’s good to understand a bit about the IC industry in the USSR.  There were many state run institutions within the USSR that were tasked with making IC’s.  These included analogs of various western parts, some with additional enhancements, as well as domestically designed parts.  In some ways these institutions competed, it was a matter of pride, and funding to come out with new and better designs, all within the confines of the Soviet system.  There were also the various Warsaw Pact countries (Bulgaria, Czechoslovakia, East Germany, Hungary, Poland and Romania), that were aligned with the USSR but not part of it.  These countries had their own IC production, outside of the auspices and direction of the USSR.  They mainly supplied their own local markets (or within other Warsaw Pact countries) but also on occasion provided ICs to the USSR proper, though one would assume an assortment of bureaucratic paperwork was needed for such transfers.

This resulted in some countries developing similar devices, at rather different times, or different countries focusing on different designs.  East Germany was all in on the Z80, Romania, Poland and Czechoslovakia made clones of the 8080, Bulgaria, the 6800 and 6502. They were though, seperate from the USSR’s own institutional system, so while East Germany had a working Z80 in the early 1980’s the USSR did not.  It is this distinction we will focus on today

This article is largely from guest author Vladimir Yakovlev, translated from Russian, and edited/expanded by me.

By the end of the 80s – beginning of the 90s, clones of the British Sinclair ZX Spectrum computer, a simple, cheap computer with a huge library of games originally released in 1982, were being distributed in the USSR. The “strapping” of the central processor instead of the original ULA microcircuit was done on small logic microcircuits of the 555 (74LS) series and the like, but the Z80 itself had to be bought from abroad. Naturally, the thought arose, to start making the processor yourself. After all, the processor itself, developed in 1976 for the microelectronic industry, was not too complicated.

In 1990, the development of an analogue of the Z80 was organized in Zelenograd near Moscow at the Scientific Research Institute of Precise Technology (NIITT) and the “Angstrem” plant. Initially, Zelenograd was conceived as a center of the textile industry, but was later reoriented to the development of electronics and microelectronics by Nikita Kruschev after he visited Silicon Valley (California, USA) in 1959. To this day, Zelenograd has retained the status of a scientific center and the informal name “Russian Silicon Valley”.

The chief designer was appointed Yuri Otrokhov, who had previously led similar developments. Otrokhov, who served as a tanker in his youth (military service being mandatory in the USSR), called the project the T34 microprocessor.

Otrokhov: “T-34VM1 is the internal designation of the KR1858VM1 processor, assigned by me at the stage of development and production in honor of my first tank, on which I learned to drive.”

Here is one of the versions of the creation of the clone, outlined by one of the employees of NIITT at that time, Boris Malashevich [1]:

“Otrokhov, like his colleagues in the department, knew how to develop original microprocessors, but they had not yet had to reproduce analogs. Therefore, the developers included specialists from NIITT divisions who are able to restore the electrical circuit of the IC according to its topology. For 9 months after four iterations, they managed to make an NMOS microprocessor T34VM1 (KM1858VM1, KR1858VM1) – a complete analogue of the Z80A microprocessor, to be made using a 2-micron technology” (The original Zilog version was on a 4 micron process).

While Otrokhov and his team worked at Angstrem to make a NMOS Z80, a similar team was working at ‘Transistor’ in Minsk Belarus to make a CMOS version, later known as the KR1858VM3.

Due to the incredible popularity and demand for the Z80, many analogue manufacturers worked without a license, so in total less than half of all Z-80 produced were licensed products from Zilog or its official partners (SGS, Mostek, etc).

From an interview with the creators of the Z80 [2]:

Faggin: Yes, we were concerned about others copying the Z80. So I was trying to figure what we could
do that that would be effective, and that’s when I came across an idea that if we use the depletion load
the mask that doesn’t leave any trace, then I could create depletion load devices that look like
enhancement mode devices. And by doing that we could trick the customer into believing that a certain
logic was implemented, when it was not. Then I told Shima, “Shima, this is the idea how to implement
traps. Put traps, you know, figure out how to do the worst possible traps that you can imagine,” and then
Shima with his mind, that was steel mind, was able to actually figure out a bunch of traps that he could
talk about.
Shima: I didn’t count [on] talking about that mostly. I placed six traps for stopping the copy of the layout
by the copy maker. And one transistor was added to existing enhancement transistors. And I added a
transistor looks like an enhancement transistor. But if transistors are set to be always on state by the ion
implantations, it has a drastic effect on very much. I heard from NEC later the copy maker delayed the
announcement of Z80 compatible product for about six months. That is what I got from NEC. And finally
a total transistor of Z80 became 8,200 while a total of transistor of 8080 was 4,800.

In the course of the design, due to the fact that the development team had specialists in both the creation of new ICs and the reproduction of analogs, Zilog’s tricks aimed at copy protection were identified and decrypted. For example, the topologist saw the 3-Input-NAND Gate element, but this element worked as 2-Input-NAND Gate. The topology and layout of the resulting clone was different, but the functionality did not differ from the original. At first, it was possible to identify such traps, making sure that the circuit was inoperable, only by examining the circuit elements inside the die using probe analyzers. But, having understood the principle of constructing traps, a mechanism for their detection was also developed. As a result, it was possible to make a full-fledged analog of the Z80, although the electrical circuit and topology of the T34MV1 had some differences.

The German Connection

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In sports, particularly Baseball, its often said that the longer a record is to say, they less impressive it is.  ‘Most Home Runs Ever’ is much more of an impressive record then ‘Most Home runs in the 7th inning against a left handed pitcher with a runner on 3rd’  Both are of course records, the first, many may even know the answer (Barry Bonds), the second? I’m sure someone can look it up but I have no idea.

So when I got this interesting commemorative AMD Opteron Sample it seems fitting to break down the record engraved on it ‘Shanghai – World’s 1st 45nm Monolithic Quad Core x86 CPU – October, 2008’  That seems impressive, and the reality is that it was (and is) and its a testament to the very hard work the design team, whose names are engraved for perpetuity on the chip, put into it.  The Shanghai was a third gen Opteron that followed the very troubled Barcelona, so it was really a make or break design for AMD.

Intel Core 2 Quad Q9100 QAVK Engineering Sample – Dual 45nm dies – Mid 2008

The most impressive aspect of the record is ‘First monolithic quad core x86 CPU.’  This was putting 4 x86 cores on a single die. Now Shanghai wasn’t the first to do this, as Barcelona had done so previously, thus the addition of ’45nm’ to the record.  Barcelona was made on a 65nm process whereas Shanghai shrank that to 45nm.  At the time Intel had the Quad-Core Clovertown Xeons (65nm) and had (in 2007) just released the Harpertown/Yorkfield Quad-Cores made on a new 45nm process.  All of these used two dual core dies in a single package. Intel was able to catch up later with the Nehalem based processors in 2009.

Was there other single die Quad-cores at the time?  What if we look outside of the realm of x86?  In 2008 IBM released the z10 quadcore processor, it was a single die, running at up to 4.4GHz (!) but it was made on a 65nm process.  Likewise, the UltraSPARC T2 was a 8-core CPU from 2007 but again, only on a 65nm process.  Freescale released the 45nm quadcore, single die P3 series P2040 PowerPC processors, but in 2010.  MIPS had the quadcore 1004K in 2008 but only on 65nm. So it seems AMD may have had a better record then they thought.

What if we stretch what we call a processor? There were at the time some fairly simple large multicores like the Tilera TILE64 (64-basic 32-bit cores) made on 45nm process, but they are less of a general purpose CPU.  Perhaps the closest is the Sony CELL Processor in the Playstation 3, which IBM was moving to 45nm in 2008 and had 1x PowerPC core + 7 SPEs. Perhaps AMD could have made a claim to the first 45nm single die CPU ever, even including non-x86 chips.

SEMICON WEST 1996 PLCC68 Memorabilia

In 1970 an industry group was started called SEMI (Semiconductor Equipment and Materials International).  They were formed to represent, as the name implies, all the various people/companies involved in making semiconductors.  This wasn’t so much the Intel’s and AMD’s but the companies that made the equipment, chemicals, and even software they used to actually design, fab, package and test chips.

In 1971 they had their first tradeshow, SEMICON WEST, at San Mateo Fairground, California.  They continue to have events around the world, SEMICON WEST is now in San Francisco (and there was a corresponding SEMICON EAST that started in 1973 in New York, but no longer exists).

SEMI not only provides an avenue for vendors and technology to be showcased, but they also work to put forth standards in industry, as well as education.  It was SEMI in the 1970’s who worked to develop standard wafer sizes, can you imagine if there was no standard sizes for such a principal component? Madness!

Lack of molded markings (usually date/country/lot would be included) suggest this was made specific for the conference.

These conferences have seminars on such compelling topics as ‘Chemical Mechanical Polishing’ and ‘Photosensitive Benzocyclobutene for Stress-Buffer and Passivation Applications.’  Today they also include vendors and information on hiring, and personnel management in the semiconductor industry, as well as safety, environmental, and education.  Certainly not as flashy as CeBIT or COMDEX, but perhaps equally if not more important.

The pictured chip was given away as swag during SEMI/WEST 1996.  Its a pretty typical PLCC68 package with the logo from that years conference.  On the back there is a complete lack of markings (even in the mold) suggesting this may have been a run specifically made for the conference, probably by a packaging vendor.