80860 > IntelA80860XP-50

Modified: April 23, 2005, 8:35 pm

Manufacturer:	Intel
Model:	A80860XP-50
Speed:	50MHz
Type:	i860
Data Code:	9424
Introduced:	1990
Transistors:	2.5 Million
Package:	262 CPGA
Process:	0.8 Micron
Architecture:	64 bit RISC
Used in:	Paragon Supercomputers and others
Description:	The Intel 80860 was an impressive chip, able at top speed to perform close to 66 MFLOPS at 33 MHz in real applications, compared to a more typical 5 or 10 MFLOPS for other CPUs of the time. Much of this was marketing hype, and it never become popular, lagging behind most newer CPUs and Digital Signal Processors in performance. The 860 has several modes, from regular scaler mode to a superscalar mode that executes two instructions per cycle and a user visible pipeline mode (instructions using the result register of a multi-cycle op would take the current value instead of stalling and waiting for the result). It can use the 8K data cache in a limited way as a small vector register (like those in supercomputers). The unusual cache uses virtual addresses, instead of physical, so the cache has to be flushed any time the page tables changes, even if the data is unchanged. Instruction and data busses are separate, with 4 G of memory, using segments. It also includes a Memory Management Unit for virtual storage. Known as the 'Cray on a chip' The chip was released in two versions, the basic XR (code name N10), and the XP (code name N11). The XP added larger on-chip caches, a second level cache, faster buses, and hardware support for bus snooping, for cache consistency in parallel computing systems. The XR ran at 25 or 40MHz, and a process shrink for the XP (from 1 micrometre to 0.8) bumped the XR to 40 and 50MHz. Both ran the same instruction set. At first the i860 was only used in a small number of very large machines like the iPSC/860 at Los Alamos National Laboratory. As the compilers improved, the general performance of the i860 did likewise, but by then most other RISC designs had already passed the i860 in performance.