ARM > IntelSA-110
Modified: May 8, 2005, 12:01 am
Model:SA-110 21281-EB
Data Code:9949
Transistors:2.1 Million
Process:0.35 Micron
Architecture:32 bit ARM RISC
Used in:Palmtops, etc HP Jornada
Description:The StrongARM was designed by DEC and bought by
Intel in 1997. It is a fully ARM compliant
device (ARM V4)

Internal phase-locked loop (PLL)
— 3.68 or 3.56 MHz External Reference
• Idle and sleep power-down modes
• Big and little endian operating modes
• 3.3 V I/O interface
• 144-pin thin quad flat pack (TQFP)
• 32-way set-associative caches
— 16 Kbyte instruction cache
— 16 Kbyte write-back data cache

The Intel® StrongARM® SA-110 Microprocessor (SA-
110), the first member of the StrongARM® family
of high-performance, low-power microprocessors,
is optimized for meeting embedded consumer
lication and portable application requirements.
Offering power-saving features, low cost, and
high performance and price/performance, the SA-
110 is a solution for high-bandwidth network
switching, intelligent office machines,
storage systems, and internet appliances, as well
as digital cameras, barcode scanners, and other
emerging consumer applications. In addition, to
delivering performance requirements in a low-
power design, the SA-110 offers compatibility
with existing ARM™ development tools and operating