Celeron > IntelCeleron950-128-100
Modified: May 7, 2005, 4:41 pm
Data Code:0130
Transistors:28 Million
Package:370 FCPGA
Process:0.18 Micron
Architecture:32 bit CISC w/ MMX
Used in:Computers
Description:The Celeron is the name of Intels value line of
CPUs. It originally started out as a PII w/ NO
L2 cache, performance was dismal at best.
So Intel decided to add 128K on die at full speed
These chips were fast, and overclocked very well.
Next Intel switched the Cleron to a coppermine
core, again with 128k of cache and eventually
a 100MHz bus.

Many of the Coppermine Celerons were PIIIs
w/ half the cache disabled. This helped
Intel sell chips who could not be validated
as a PIII.

-Covington - 0k of cache - SEPP Package
7.5 Million Transistors

-80524 Mendocino (Celeron-A) - 0.25u 128k on chip
19 Million Transistors

-Mobile Celeron - 128k - MMC-1/2 Package
19 Million Transistors

-Coppermine-128 - 0.18 Micron 128K on die - SSE
known as Celeron-II
28 Million Transistors

-Mobile Coppermine Celeron - 128k Cache Low Voltage
28 Million Transistors

-Coppermine-T - Tualatin core 256k Cache
Known as Celeron-III
28.1 Million Transistors

-Mobile Coppermine-T - 256k ond ie, Low Voltage
28.1 Million Transistors
Core: Coppermine
Cache: 128k
FSB: 100