Itanium > Intel80541KZ8004M-QBE9ES
Modified: June 3, 2005, 7:09 pm
Data Code:0048
Transistors:25 Million + 300 Million for Cache
Package:418 Hybrid Socket
Process:0.18 Micron
Architecture:IA-64 EPIC VLIW
Used in:High-End Servers
Description:The first Itaniums ran at 733 and 800MHz. Itanium
is Intel's first true 64-bit chip, and uses their
EPIC (Explicitly Parallel Instruction Computing)
instruction set (IA-64 computing). The EPIC
instruction set is heavily compiler dependant.

The Itanium is capable of 6 gigaflops. It has 4
integer units, and 2 floating point units.
Itanium comes with 2MB or 4MB of L3 cache. Also,
it feature L1 (32K - 16K instruction, 16K data -
4-way set associative, 32-byte lines) and L2
(96KB dual-ported 6-way unified, 64-byte lines)
cache on chip, with L3 cache in the Itanium
package (which is smaller than 3x5" index card),
but not on the chip. OEM's can also add a 4th
level of cache, or L4 cache.

The Itanium is capable of dealing with up to 16
GB of main memory. It shipped initially with the
460GX chipset, and used standard PC100 SDRAM at

The Itanium contains a 10-stage instruction
pipeline. As for registers, the Itanium has 128
floating point, 128 integer , 64 predict, and
finally 8 branch registers

In practice the performance of the Itanium
was lackluster, mainly because it was highly
compiler dependent. If the code was not
perfectly compiled for it it would be very slow.
However, if the code was clean, it would fly.
But code is like pigs, rarely clean, so the
Itanium is fast, when pigs fly.
L3 Cache: 4096k
Bus: 133MHz
This is an early Engineering Sample.