Stratus XA/R (courtesy of the Computer History Museum)

Making the rounds this week is the Computer World story of a Stratus Tech. computer at a parts manufacturer in Michigan.  This computer has not had an unscheduled outage in 24-years, which seems rather impressive.  Originally installed in 1993 it has served well.  In 2010 it was awarded for being the longest serving Stratus computer, then being 17 years.  Phil Hogan, who originally installed the computer in 1993, and continues to maintain it to this day said in 2010  “Around Y2K, we thought it might be time to update the hardware, but we just didn’t get around to it”  In other words, if it’s not broke, don’t fix it.

Stratus computers are designed very similar to those used in space.  The two main difference are: 1) No need for radiation tolerant designs, let’s face it, if radiation tolerance becomes an issue in Michigan, there are things of greater importance than the server crashing and 2) hot swappable components.  Nearly everything on a Stratus is hot-swappable.  Straus servers of this type are based on an architecture they refer to as pair and spare.  Each logical processor is actually made from 4 physical CPU’s.  They are arranged in 2 sets of pairs.

Stratus G860 (XA/R) board diagram. Each board has 2 voting i860. (the pair) and each system has 2 boards (the spare).  The XP based systems were similar but had more cache and supported more CPUs.

Each pair executes the exact same code in lock-step.  CPU check logic checks the results from each, and if there is a discrepancy, if one CPU comes up with a different result than the other, the system immediately disables that pair and uses the remaining pair.  Since both pairs are working at the same time there is no fail-over time delay, it’s seamless and instant.  The technician can then pull the mis-behaving processor rack out and replace it, while the system is running.  Memory, power supplies, etc all work in similar fashion.

These systems typically are used in areas where downtime is absolutely unacceptable, banking, credit card processing, and other operations are typical.  The exact server in this case is a Stratus XA/R 10.  This was Stratus’s gap filler.  Since their creation in the early 1980’s their servers had been based on Motorola 68k processors, but in the late 1980’s they decided to move to a RISC architecture and chose HP’s PA-RISC.  There was a small problem with this, it wasn’t ready, so Stratus developed the XA line to fill in the several years gap it would take. The first XA/R systems became available in early 1991 and cost from $145,000 to over $1 million.

Intel A80860XR-33 – 33MHz as used in the XA/R systems. Could be upgraded to an XP.

The XA is based on another RISC processor, the Intel i860XR/XP.  Initial systems were based on 32MHz i860XR processors.  The 860XR has 4K of I-cache and 8K of D-cache and typically ran at 33MHz.  Stratus speed rating may be based on the effective speed after the CPU check logic is applied or they have downclocked it slightly for reliability. XA/R systems were based on the second generation i860XP.  The 860XP ran at 48MHz and had increased cache size (16K/16K) and had some other enhancements as well.  These servers continued to be made until the Continuum Product Line (Using Hewlett Packard “PA-RISC” architecture) was released in March of 1995.

This type of redundancy is largely a thing of the past, at least for commercial systems.  The use of the cloud for server farms made of hundreds, thousands, and often more computers that are transparent to the user has achieved much the same goal, providing one’s connection to the cloud is also redundant.  Mainframes  and supercomputers are designed for fault tolerance, but most of it is now handled in software, rather than pure hardware.

HP 12152-60002 A700 Phoenix Processor – 4x AMD AM2903 (1820-2377)

The Lighting processors of the HP A600 and A600+ were good performing for 1982.  They filled the entry and mid range slots of the HP 1000 A Series quite well.  The additional floating point support of the A600+ in 1984 helped considerably as well, but what was needed for truly better performance on the high end was hardware math support.  While the HP A600 took only 9 months to design and release, the A700, released at the same time, took somewhat longer.  The A600 was based on the AMD 2901, which had been released way back in 1975.  The A700 Phoenix was based on its successor, the AM2903.  The 2903 added a few important features to the bit-slicer.  Hardware multiply and divide support,support for more registers, and easier ways to access them, and parity generation.  This is why the A700 took longer to design, the A600 design was begun half way through the A700 to fill the lower end, where the features of the 2903 wouldn’t be as missed.

The A700 performs at the same 1 MIPS as the A600 but supports 205 standard instructions (compared to 182 for the A600 and 239 for the A600+).  It adds more register reference instructions, dynamic  mapping, I/O and more math based instructions.  Cycle time is actually slightly slower, 250ns compared to 227ns for the A600 but the 2903 allows more efficiency making up for the difference.  A typical FMP instruction take 13.75-25.25 microseconds compared to 16.6-26.6 on the 2901 powered A600.  This is a direct result of the hardware multiply hardware included in the 2903.  The A600+, with its faster 2901C’s completes the same instruction in 17-21.1 microseconds, FASTER then the A700. But the A700 has a trick up its sleeve….

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HP A600+ Processor Board. 4x AMD AM2901CDC (1820-3117) 1x AMD AM2904DC and 1x AMD AM2910 (1820-2378). Some versions used 2901’s from National Semiconductor.

In the early 1960’s HP was exploring connecting computers to its various instruments, for control, monitoring, and logging.  The DEC PDP-8 had come out in 1965 as perhaps the first mini-computer and could be used to control HP’s instrument’s.  However, HP determined that it would actually be easier, and faster to design and build their own computers rather than work with DEC.  DEC probably didn’t see HP’s interest as important enough to make it easy (some interfacing for I/O etc would have to be done).  It worked out well for HP however, as this pushed them into an entirely new, and emerging market.

In 1966 HP released the 16-bit HP 2100 (later to be renamed the HP 1000 series).  It was a design that had begun under Union Carbide’s Data Systems Inc, a company HP had recently acquired.  This gave HP a head start, and allowed them to evolve the design to meet their needs (at the time mostly to control instruments).  When released it included not only the hardware but a completely function software suite as well, including a FORTRAN compiler.  They initially ran with a 10MHz clock and a 1.6usec memory cycle time.

Throughout the 1970’s the design evolved, and would lead to many computers.  The 98xx desktop systems using HP’s NMOS BPC Hybrid processor were based on the HP 1000 series.  The design was a fairly simple accumulator based architecture with 2 16-bit accumulators (A and B) and a 15-bit PC and 68-base instructions.  The first version was directly programmed but all subsequent versions were microprogrammed, making alterations and additions to the instruction set much easier, a feature that became important in keeping the HP 1000 around.

The A series were the HP 1000’s of the 1980’s.  Development began around 1980 and the first computers, the A600 and A700, were released in 1982.  These were some of the first LSI based processors for the line.  THe A600 processor was called the ‘Lightning.’  The name “Lightning” came from the Mark Twain quote “Thunder is good, thunder is great, but it is lightning that does all the work.” “Thunder” was a reference to the PDP 11/23, one of DEC’s newer machines at the time.  HP had went from considering using DEC’s computers to run instruments, to the 4th largest maker of such computers in only a decade.  Certainly a fact not lost on either company.

The A600 is an interesting design, it is of course microprogrammed, and is based on AMD AM2901B bit-slice processors, supported by a 2910 microsequencer, and the 2904 status/shift control unit.  The rest of the board is Schottky TTL, PALs, FPLAs. and ROMs.  Each HP 1000 instruction is microcoded into a 56-bit instruction for controlling the 2901’s 2904 and 2910.  These 56-bit instructions directly operation on the processor.  Certain bits interface with certain parts of each chip, so they are directly executed.

A600 – 56-bit microinstruction word directly operates on the hardware (click for LARGE version)

A series of PAL’s contain the microcoding, allowing for easy updating (at the time).  A standard A600 executed 182 standard HP 1000 instructions.  It could do so at a rate of 1 MIPS, with a cycle time of 227 nanoseconds.

Each 2901 is a 4-bit slice processor, and contains 4-bit registers and ALU’s.  The HP 1000 A and B registers are mapped directly to the R0 and R1 registers of the 2901’s and the Program counter resides in R15.  The PAL’s determine what HP 1000 instruction is being executed, and decode it into the proper 2901 assembly code, building the 56-bit instruction word.  This is one of the best examples of how the AMD 2901 (and other bit slicers) were designed to be used.  The end user has no idea, or need to know what is executing their HP 1000 code.  Its is decoded and send to the bit slicers for processing which then return the results to the proper place.  If new functions are needed a new processor does not need to be designed, simply add additional PAL code to decode the new instructions.  And that is exactly what HP did….

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HP 3000 Series 33 – 16-bits 11MHz. They were integrated into the desk, with a 20MB hard drive on the left, and the computer on the right (with a 1.2MB 8″ Floppy Drive)

In 1972 HP introduced the HP 3000 line of minicomputers.  Mini of course meaning they didn’t take up the entire room.  They competed against the likes of the DEC PDP-11 and the TI-990.  Original called the System/3000 (apparently to compare favorably to the IBM System/360) they were renamed the HP 3000.  These were 16-bit computers employing a stack based design,  They had no general purpose registers, all operations operated directly on one of several stacks.  The first models were designed using bipolar discrete logic and ROM for the microcoding.  This allowed for good performance but was expensive and large.  Just the processor for the high end Series III of 1978 was 9 boards.

The Series 33 (and the smaller series 30) were to be cost reduced versions, to slot in between the high end Series III and the newly introduced HP 300 microcomputer.  In order to do this those 9 boards for the processor needed to be greatly simplified.  HP engineers decided to use a processor they had already, the CPU from the HP 300 Amigo.  The HP Amigo was a bit of a disaster for HP, after 5 years of development, including

1AB4-6003 RALU -Silicon on Sapphire – 8000 Transistors

designing an entirely new processor it was a failure in the market, suffering from management and politics more then from a technical standpoint (it was not file system compatible with the 3000 line and that caused some concerns).  After being released in 1978 it made only around $15 million in sales and was canceled after a short time.

Part of that 5 year development was for its 16-bit VLSI processor.  In order to get the speed needed for the HP 300 and at a low price, the pressor needed to be a VLSI design (a few chips rather then a few boards).  In order to fit in a smaller pedestal cabinet it needed to energy efficient and heat efficient as well.  HP’s engineers decided to use a Silicon On Sapphire (SoS) CMOS design, a process HP had some great experience with in the MC2 processor.  SoS is a form of Silicon on Insulator, a manufacturing method that is very common in today’s IC’s (using Silicon Dioxide).  Instead of an IC being made on a pure silicon wafer, the silicon is deposited on a wafer of sapphire.  Sapphire is an excellent insulator which wels reduce leakage currents, as well as spurious currents from such things as radiation.  Radiation tolerance is perhaps what SoS became known for most, but its low power performance was what HP was after in the 1970’s.

Die shot of the RALU with labels.

The processor for the HP 300 was designed into 3 separate IC’s, totaling 20,000 transistors (some documentation says 25,000) and running at a clock of 11MHz.  The processor control unit (PCU 1AB2-6003) chip generates microinstruction addresses that control the other two chips: the register, address, skip, and special (RASS 1AB3-6003) chip and the register, arithmetic, and logic unit (RALU 1AB4-6003) chip.

The PCU contains 5000 transistors and handles the microsequencing, clock generation, and a sub-routine save stack.  Clock generation is interesting as its single phase, and variable.  The PCU can lengthen or shorten the clock period as needed.  If a memory operation needs longer to complete the PCU simply holds the lock period longer.  Data path functions are handled by the RASS and RALU chips.  The RASS contains about 7000 transistors and contains a register file for the second operand to the RALU as well as address generation and skip logic.  The largest of the chips is the RALU.  It handles all of the standard ALU functions as well as hardware multiply/divide.  It also contains 16 registers: 8 general purpose registers, and 8 for address storage.  Together these three chips form the CPU of the HP 300 and consume only 1Watt of power.  The processor is a microcoded design so the actually instruction set resides in ROM, in this case on a separate board.  In the case of the HP 300 this also allowed the I/O processor duties to be microcoded into the general processor, eliminating another subsystem.

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National 2758 – Intel 2758 (1979) – Intel 2758 (1980) – Click for larger version

Recently I got in some nice 2758 EPROMs.  The 2758 was a 5V 8k EPROM and really the first of the standard EPROMs (with industry standard pinouts, voltages, etc).  The original 2708 required 3 supplies (5V, -5V and 12V) while the 2758 required only +5VDC.  EPROMs are particularly nice as due to the fact that they need a window to allow UV light in for erasure, you can also have a clear shot of the die (in most cases).

Two things caught my eye on these 3 EPROM’s.  First, the National Semiconductor 2758 die looked suspiciously like the Intel die.  This isn’t too unusual as National was one of Intel’s primary second sources throughout the 1970’s.  Intel did not have the best fab’s early on so second sourcing was a must.  As a product of this some strange things happened, such as Intel die’s being in National labeled parts (though the reverse is not known to have happened).

Intel 2758 w/ 2716 die

The second thing you can see in the picture is the difference in die structure between the otherwise seemingly same Intel 2758’s.  One has bonding wires on all 4 sides, while the second one has bonding wires only on the top and bottom of the die, and a completely different layout to the die.  My first suspicion was that the Intel and National may both be the same die, so I put them on my scanner (I REALLY need  a microscope). At 4800dpi (or 9600dpi on one) you can see that they are in fact different dies, and both are not 2758 dies….

National 2758 also using a 2716 die

Both are actual 2716 dies! We saw this several years ago with 2708s being used as 2704’s as well as in Soviet designs.  The third die is a 2716 die as well.  All Intel (and National) did was leave one address line unused (tied to ground in this case).  Its likely these dies had a defect so the affected area was effectively disabled by not using that address line.

C2758 S1865 – Defective 2716 die using only the upper 8k

The difference in the Intel dies is also interesting.  Early in the production of the 2716 Intel changed the die layout to increase density. That’s why one die has the bonding wires on all 4 sides and the newer die only on top and bottom (which made assembly faster and more reliable

as well as increasing density).  The 2716 was released BEFORE the 2758, the 2758 being almost an afterthought, it is very likely that ALL 2758 dies are actually 2716 dies, as it would make little sense for Intel to create a separate mask set for a product that was likely to be low volume.  The 2758 data sheet lists pin 19 as A_R (Address reference) and specifies it to be driven low, or for the S1865 driven high.  Pin 19 on a 2716 is A₁₀ so A_R on the 2758 is simply selecting the lower 8k or for the S1865 the upper 8k.  Being as there was 2 versions of the 2758 using different parts of the die, its clear Intel was using defective 2716 die to make the 2758, at least early on.  Later documentation simply has Pin 19 listed as GND.

As a side note, the CPU Shack REALLY needs a microscope, sorry for the blurry photos from the scanner.

GRAPE-6 Processor – 90MHz -2000

Understanding the movements of the stars has been on mankinds mind probably since we first stared into the sky.  Through the ages we can predict where a star or planet will be in the sky in the next few months, years, even hundreds of years, but to be able to predict the exact orbital details for ALL time is rather more tricky.

This helps understand how planetary systems form, and the conditions that make that possible.  It allows us to see what happens when two massive black holes pass each other by, will the merge? will they orbit? will one go rogue?  These are interactions that take millions of years, and thus we need to calculate the gravitational forces very accurately. This isnt a terribly hard problem for two bodies, and is doable for three with little fuss, but for numbers of bodies greater then that, the calculations grow rapidly, on the order of N²/2.

In the late 1980’s Tokyo University began work on developing a computer to calculate these forces.  Every gravitational force had to be be calculated with its effects on every other body in the system.  These results were then fed to a commodity computer for summation and final results.  This made the Tokyo project a sort of Gravity co-processor, or as they called it a Gravity Pipeline, GRAPE for short.  The GRAPE would do the main calculations and feed its results to another computer.

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ZTFM  S555C1 – Hobbyist edition 2708 EPROM – 1983

Thanks to the input of a reader I updated the East German CPU page to be much more accurate as to the various institutions that existed, and their respective logos.  There were institutions in three different cities (Erfurt, Frankfurt, and Dresden), and they had amongst them 7 different names and a variety of logos.

It helps to remember that IC’s were made different in East Germany.  There was not so much corporations as we think of them in the West such as Intel or AMD that made this or that.  In East Germany (and the USSR) IC’s (and most everything else) were made by institutions, that were typically a government organization, or sanctioned by the government to do/make certain things.  These could be changed, consolidated, opened/closed at the whim of the government resulting in a lot of confusion in identity.  Add to that the changes brought with the fall of communism, and these institutions transition to modern corporation and you get some very interesting collecting opportunities.

The updated page should help ID’ing them a bit easier.

Cadence Palladium II Processor MCM 1536 cores – 128MB GDDR – Manufactured by IBM

Several years ago we posted an unusual MCM that’s purpose was a mystery.  It was clearly made by IBM and clearly high end.  While researching another mystery IBM MCM both of their identities came to light.  The original MCM is an emulation processor from a Cadence Palladium Emulator/Accelerator system.

In the 1990’s IBM had been working on technology to make emulating hardware/software designs more efficient as such designs got more complicated.  At the time it was most common to emulate a system in an FPGA for testing, but as designs grew more complex this became a slower and slower process.  IBM developed the idea of an emulation processor.  This was to be known as CoBALT (Concurrent Broadcast Array Logic Technology).  It was licensed to a company called QuickTurn in 1996.  At its heart the QuickTurn CoBALT was a massively parallel array of boolean logic processors.  Boolean processors are similar to a normal processor

Here is a flipped (and very rough) die from a Palladium II. You can make out the very repeating design of the 768 boolean processors.

but only handle boolean data, logic functions such as AND, OR, XOR, etc.  Perhaps the most well known, is the boolean sub-processor that Intel built into the 8051, it excelled at bit manipulation.  The same applies for the emulation processors in CoBALT.  Each boolean processor has at its heart a LUT (Look Up Table), with 8-bits to encode the logic function (resulting in 256 possible logic function outputs) and the 3 gate inputs serving as an index into the LUT, as well as the associated control logic, networking logic, etc.

A target design is compiled and emulated by the CoBALT system.  The compiling is the tricky part, the entire design is broken down into 3-input logic gates, allowing the emulator to emulate any design.  Each processor element can handle one logic function, or act as a memory cell (as many designs obviously include memory).  The CoBALT had 65 processors per chip, and 65 chips per board, with a system supporting up to 8 boards.  This 33,280 processor system could compile 2 Million gates/Hour.  The CoBALT plus sped this up a bit and supported 16 boards, doubling capacity and added on board memory.

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Signetics 2650I – Original Version from May of 1976

The Signetics 2650 processor has always been described as ‘very mini-computer like’ and for good reason, it truly is very minicomputer like in design.  It is an 8-bit processor released in July of 1975 made on an NMOS process.  The 2650 has a 15-bit address bus (the upper bit (16) is reserved for specifying indirect addressing) allowing addressing of up to 32K of memory.  It has 7 registers, R0, which is used as an accumulator, as well as 2 banks of 3 8-bit registers accessed.  The 2650 supports 8 different addressing modes, including direct, and indirect with autoincrement/decrement.  Its clearly a mini-computer design and there is a reason for that, it was based on one.

The 2650 is very closely based on the IBM 1130 mini-computer released in 1965.  Both use 15-bit addressing, many addressing modes, and a set of 3 registers (Signetics added support for 2 banks of 3,  The Signetics 2650 is often noted for its novel use of a 16-bit PSW status register, but this too is from the 1130, which used a 16-bit Device Status Register for talking with various I/O components.  So why would Signetics base a processor released in 1975 on a 1965 mini-computer?

Because the 2650 was not designed long before it was released.  J. Kessler  was hired by Signetics in 1972 in part to help design an 8-bit processor.  Kessler was hired by Jack Curtis, (Of Write Only Memory fame) from…IBM. Kessler designed the architecture very similar to the IBM 1130 and Kent Andreas did the silicon layout.  The design contains 576 bits of ROM (microcode mainly), ~250 bits of RAM (for registers, stack, etc) and about 900 gates for logic.  Clock speed was 1.25MHz (2MHz on the -1 version) on a ion implanted NMOS process, very good for 1972 (this was as fast as the fastest IBM 1130 made), but Signetics was tied up working with Dolby Labs on audio products (noise canceling etc) and didn’t have the resources (or perhaps the desire) to do both, so the 2650 was pushed back to 1975.  In 1972 the IBM 1130 it was inspired by was still being made.  If the 2650 had been released in 1972 it would have had the Intel 4004 and 8008 as competition, both of which were not easy to use, and had complex power supply and clocking requirements.  The 2650 needed a 5V supply, and a simple TTL single phase clock.

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ARM946E on a Chartered Semiconductor 0.18u Process

ARM is one of the most popular RISC cores used today, and has been for over a decade now.  ARM is an IP company. They license processor designs/architectures for others to use, but do not actually manufacturer the processors themselves….or do they?

ARM offers a variety of cores, and licenses them in a variety of different ways.  There are, in general, three main ways to get an ARM design.  Larger companies with may resources (such as Apple, Broadcom, or Qualcomm) will purchase an ARM architecture license.  This isn’t specific to any ARM core in particular (such as say a ARM946) but the entire ARM architecture, allowing these companies to design their own ARM processors from the ground up.  This takes a lot of resources and talent that many companies lack.

Second, ARM offers RTL (Register Transfer Level) processor models, these are provided in a hardware programming language such as VHDL or Verilog.  They can be dropped into a design along with other IP blocks (memory, graphics, etc) and wrapped with whatever a company needs.  This is a fairly common method, and typically the lest expensive.  It does require more work and testing though.  Designing a chip is only part of the process. Once it’s designed it still must be fab’d.

ARM7EJ-S on a TSMC 0.18u Process. Wafer #25 from June 2003

ARM also offers ARM models that are transistor level designs, pre-tested on various fab processes.  Pre-tested means exactly what it sounds like. ARM designed, built and had them manufactured, fixing any problems, and thus giving the ability to say this core will run at this speed on this fab’s process.  Testing and validation may often go as far as testing a particular fab’s particular process, in a particular package.  Its more work, and thus cost more, but these make for drop in ARM cores. Want to use a ARM946 core, on a TSMC 0.18u process in a lead free Amkor BGA package? Yah ARM’s tested that and can provide you with a design they know is compatible.  This allows extremely fast turn around from concept, to design to silicon.

In the below picture (click to enlarge) you can see a large variety of ARM cores from the early 2000’s. They span ARM7, ARM9, ARM10 and ARM11 designs.  Each is marked with info as to what exactly it is.  The core name, the revision (such as r2p0, meaning major revision 2, pass/subversion 0) as well as the Fab (TSMC, UMC, SMIC, Chartered) and the design node (all of these are either 0.18 or 0.13u processors).

21 Various ARM design tet chips from TSMC, UMC, Charted, covering many ARM cores.

Also noted on some is the exact wafer the die was cut from, this is typical on VERY early production tests, usually first run silicon, so they can identify any physical/manufacturing defects easier.  Some design modifications have little to do with the processor itself, but are done to increase yields on a given process/node.

ARM926EJ on a UMC 0.13u Process. 

Package type (in this case most are Amkor BGA) and other features are noted.  Many say ‘ETM’ which is ARM’s Embedded Trace Macrocell, a debugging tool that allows instruction and date traces of an in operation core, very useful for debugging. ARM offers ETM for each of their processor types (ETM9 for example covers all ARM9 type cores) and itself has a revision number as well.

Some of these chips come in an interesting BGA package. The package has a removable die cover for inspection/testing (and possibly modification). Note the large die in the ARM926EJ on the left, though the processor core itself is very small (its in the upper left only a few square mm).  This is done to facilitate bonding into the package, In this type of package there wouldn’t be any way to connect all the bonding wires to the very tiny ARM core, so the die has a lot of ‘wasted’ space on it.

So does ARM make processors? Yup! but only for internal use, to help develop the best possible IP for their clients.