OSIRIS-Rex: RAD750 to Bennu

The Apollo Group  carbonaceous asteroid Bennu is a potential Earth impactor, with a 0.037% likelihood of hitting earth somewhere between 2169 and 2199.  Bennu is thought to be made of materials left over from the very early beginnings of our solar system, making researching them a very tantalizing proposition.  Rather than wait for the small chance of Bennu delivering a sample to Earth in 150 years the thoughtful folks at NASA decided to just go fetch a bit of Bennu.  Thus is the mission of OSIRIS-REx which was launched a few days ago (Sept 8, 2016) aboard an Atlas V 441 as an $850 Million New Frontiers mission.

Somewhat surprisingly there is scant details about the computer systems that are driving this mission to Bennu.  OSIRIS-REx is based on the design of the Mars Reconnaissance Orbiter (MRO), MAVEN and Juno, and thus is based on the now ubiquitous BAE RAD750 PowerPC processor running the redundant A/B side C&DH computers.  This is the main ‘brain’ of the Lockheed Martin built spacecraft.  Of course the dual RAD750s are far from the only processors on the spacecraft, with communications, attitude control, and instrumentation having their own (at this point unfortunately unknown) processors.

REXIS Electronics: Virtex 5QV – Yellow Blocks are Off the Shelf IP, Green Blocks are custom by the REXIS Team. Powered by a Microblaze SoftCore.

One instrument in particular we do know a fair amount about though.  Regolith X-ray Imaging Spectrometer (REXIS) is a student project from Harvard and MIT. REXIS maps the asteroid by using the Sun as an X-ray source to illuminate Bennu, which absorbs these X-rays and fluoresces its own X-rays based on the chemical composition of the asteroid surface. In addition REXIS also includes the SXM, to monitor the Sun’s X-Rays providing context to what REXIS is detecting as it maps Bennu.  REXIS is based on a Xilinx Virtex-5QV Rad-Hard FPGA.  This allows for a mix of off the shelf IP blocks, and custom logic as well. The 5QV is a CMOS 65nm part designed for use in space.  Its process, and logic design are built such as to minimize any Single Event Upsets (SEU), and other radiation induced errors.  It is not simply a higher tested version of a commercial part, but an entirely different device.   Implemented on this FPGA is a 32-bit RISC softcore processor known as Microblaze.  The Microblaze has ECC caches implemented in the BRAM (Block RAM) of the FPGA itself and runs at 100MHz.

It will take OSIRIS-REx 7 years to get to Bennu, sample its surface, and return its sample to Earth.  By the time it gets back, the RAD750 powering it may not be so ubiquitous, NASA is working on determining what best to replace the RAD750 with in future designs.  Currently several possibilities are being evaluated, including a QuadCore PowerPC by BAE, a QuadCore SPARC (Leon4FT), and a multi-core processor based on the Tilera architecture.  As with consumer electronics, multi-core processors can provide similar benefits in space of hogher performance and more flexible power budgeting all with the added benefit (when design for such) of increased fault tolerance.

Intel A80486DX SXE19 Engineering Sample – May 1989

The Intel 80486 was announced at COMDEX in April 11th 1989, justy 3 years after the 80386 hit the market.  The 80486 was really a greatly enhanced 80386. It added a few instructions, on-chip 8KB Write-Thru cache (available off chip on 386 systems) as well as an integrated FPU.  Instruction performance was increased through a tight pipeline, allowing it to be about twice as fast as the 80386 clock for clock.  Like the 80386 the 80486 was a CISC design, in an era when the RISC processor, in its may flavors, was being touted as the future of ALL computing.  MIPS, SPARC, and ARM all were introduced in the late 1980’s.  Intel themselves had just announced a RISC processor, the i860, and Motorola had the 88k series.  Intel in fact was a bit divided, with RISC and CISC teams working on different floors of the same building, competing for the best engineering talent.  Would the future be CISC, with the 80486? Or would RISC truly displace the CISC based x86 and its 10 years of legacy?

This dilemma is likely why Intel’s CEO, Andy Grove, was nearly silent at COMDEX.  It was only 4 years previous the Mr. Grove, then as President, made the decision to exit the memory market, and focus on processors, and now, a decision would soon loom as to which type of processor Intel would focus on.  Intel eventually ditched the i860 and RISC with it, focusing on the x86 architecture.  It turns out that ultimately CISC vs RISC didn’t greatly matter, studies have shown that the microarchitecture, rather then the Instruction Set Architecture, is much more important.

Intel A80486DX-25 – SX249 – B4 Mask from Sept 1989 with FPU Bugs

Whether due to the competition from the i860 RISC team, or knowing the markets demands, the 80486 team knew that the processor had to be executed flawlessly.  They could ill afford delays and bugs.  Samples of the 80486 were scheduled to be released in the 3rd quarter of 1989 with production parts shipping in the 4th quarter.  The above pictured sample is from May of 1989, a quarter ahead of schedule.  Production parts began to ship in late September and early October, just barely beating the announced ship date.

Perhaps due to the rush to get chips shipping a few minor bugs were found in the FPU of the 486 (similar to bugs found in the FPU of the 387DX).  Chips with the B4-Mask revision and earlier were affected (SX249).   These bugs were relatively minor and quickly fixed in the B5 mask revision (SX250), which became available in late November of 1989, still within Intel’s goal of the 4th Quarter.

The 80486 was a success in the market and secured CISC as the backbone of personal computing.  Today, the CISC x86 ISA is still used, alongside the greats of RISC as well.

Motorola XC6801L – Early White ceramic package from early 1979. XC denotes a not fully qualified part.

A microcontroller (or microcomputer) is a CPU, with additional on-board peripherals, usually containing RAM, ROM, and I/O as to serve as a single (or close to single) chip solution for a computer system.  As the program space is typically small, they were designed and used for high volume, low cost, simple applications.  Today we would refer to them as embedded applications.  The Motorola MC6800, released in 1974 was a decent 8-bit processor.  It was however not inexpensive (a fact not lost upon one of its designers, Chuck Peddle, who left to design the 6502).  Initial pricing for the MC6800 was $360, dropping to $175 the next year.

For embedded use, prices needs to be in the few dollars range, with as little chips as possible required for a design.  By 1977 Motorola had a solution, the MC6802.  This MC6802 was an enhanced MC6800 128-bytes of RAM and an on-board clock-generator.  When combined with the MC6846 (which provided ROM, I/O and Timers) a complete system could be built.  Defective MC6802s were often sold as RAM-less MC6808s.

Motorola MC6802L – Dated March of 1978. The 6802 had 64-bytes of RAM and no ROM.

The MC6802 was followed by the more complex MC6801, which integrates the features of the MC6846 on die, making a true 8-bit single chip microcomputer.  Most sources refer to the MC6801 being released in 1978, however it was actually released in 1977, likely at the same time, or similar as the MC6802.  US Patent Application US4156867 filed on September 9th of 1977 references both processors.  GM was to be the lead customer for the MC6801, it was the MCU of choice for the digital trip meter (TripMaster) of the 1978 Cadillac Seville.  The 1978 Seville began production on September 29, 1977 using a 6801 made on a 5.1um NMOS process.  It is likely that all of the first production of the 6801 was reserved for GM, and it wasn’t until 1978 and later that Motorola began to market it (it begins to show up in Motorola marketing only in 1979).  In 1979 the MC6801 also switched to a 3.9um HMOS process, which likely increased yields and decreased costs.  The TripMaster was a $920 factory option that proved to be rather unpopular, likely due to it adding nearly $1000 in cost to a $14,000 car.

Motorola MC68701U4L-1 1987 6801 with upgraded RAM/ROM and Timers

This lack of early availability, coupled with the fact that while capable, the 35,000 transistor 6801 wasn’t particularly inexpensive led it to have very little success in the market.  The EPROM version, the MC68701 in fact is much more common, likely due to the fact that it was used in lower volume products, where cost wasn’t such an issue.  In 1979 Motorola attempted to remedy this by releasing the MC6805 series.  This was designed from the ground up to be low cost.  The first versions had half the ROM and half the RAM as the 6801, while keeping the I/O.  They were also available in CMOS (as the MC146805).  They were inexpensive, and highly functional, and were widely used.  The 6805 continues to see use today as the 68HC05 and 68HC08 series.

Motorola XC68HC11A0FN – 1987 – Preproduction, Enhanced 6801

The MC6801 was not, however, done.  By this time manufacturing had improved, allowing costs to be lower.  Motorola released an upgraded 6801, the MC6801U4 which expanded the timer functions, increased the ROM to 4K, and increased the RAM to 192-bytes.   In 1985 the MC6801 was upgraded again, a second 16-bit index register was added, as well as true bit-manipulation instructions.  The Motorola MC68HC11, the name change reflecting the greatly enhanced core, was made in many varieties with different sizes of RAM, ROM, and EEPROM. The MC68HC11A8 was also the first MCU to integrate EEPROM on die, in this case, 512 bytes worth.  The MC68HC11 series, and its 68HC12 and 16 successors, continue to be made, and used today, ironically, frequently in automotive applications, where the original MC6801 failed to be as great of success as Motorola dreamed of..  GM took the 6801 design and under license from Motorola, extensively modified it (along with the 6803), using external RAM and ROM, and less of the integrated peripherals, and used this custom version for their ECUs.  Some later 1980s cars used a Hitachi HD6801 version for their ECU (such as Subaru).

The CPU Shack is pleased to now offer test systems for testing the famous Intel 8086 and 8088 processors.  They also support testing of the 8087 FPU, as well as the NEC variants (V20/V30).  As an added bonus, an expansion is included for testing the i186/i188 processors as well.

Of course the original NMOS,  and later CMOS versions are supported from many manufacturers.

Head on over to the MCS-86 Test System page for more information and to order your system.

AMD 486 processor. Note the logo in the lower right corner. Package is from Kyocera (Click for larger version)

What do all 3 of these things have in common? And what in the world do they have to do with computer processors (ok modern oscilloscopes and cell phones DO have CPUs in them but spark plugs?). Tektronix was started here in Oregon in 1946 making oscilloscopes and other test equipment.  Throughout the last 70 years they have continued to do so, but along the way they also began to make everything needed to manufacture the final equipment they sold.  Design/simulation software, PCB manufacturing, IC manufacturing, displays, and even the packaging used for IC’s.  In recent years many of these vertically integrated operations have been spun off, but they do still maintain some.

Tektronix packaging options from the early 1990’s (Click for larger version)

When an IC manufacturer (such as Intel, AMD, etc) designs/builds an IC what they typically are creating (or having made in the case of fabless companies) is the silicon die itself.  This little piece of silicon contains the millions of transistors needed to perform whatever task its made for, but for most uses that silicon die needs to be packaged to be useful.  A sliver of silicon is hard to work with and integrate into designs, a package provides the routing of wire/leads to the die, as well as protects it from the environment, while dissipating any heat it generates.

IC manufactures do not typically make their own packages, they are either contracted out or bought off the shelf.  Tektronix is one of several companies that makes and sells IC packages.  The pictured display is a sample of some of the packaging types they offered.  You can recognize some of the more common packages, as well as some more specialty ones such as the ‘POWER TAB’ that was used in analog equipment frequently (like audio amplifiers etc).

Anam/Amkor Test package

Tektronix isn’t the only company that offers packages for IC.  Perhaps the two largest are NGK and Kyocera.  Both have extensive experience with ceramics, a material very useful in IC packages.  Developing high strength, high temperature ceramics for spark plugs, isn’t so much different from designing the same for a high end processor.  Kyocera started life making ceramic insulators, well before ever getting into cell phones (in 2000) and ceramic packaging continues to be their core business.

Often times assembly and test of a IC is handled by yet another company.  Many companies (such as Amkor) entire business is based on taking IC dies from one company, assembling them into packages from another, testing them, and shipping them.  So next time you look at a CPU and read its makers name boldly written on its top, there is a good chance that that name had but one part in that IC.

Juno – RAD750 Powered Mission to Jupiter

NASA’s Juno mission to Jupiter arrives in just about a day, after a 5 year journey that began in August of 2011 aboard an Atlas V rocket.  The Juno mission is primarily concerned with studying the magnetic fields, particles, and structure of Jupiter.  Finding out how Jupiter works, and what its core is made of are some of Juno’s goals.  None of the experiments need a camera, but NASA decided, in the interest of public outreach and education, that if you are going to spend $1 billion to send a probe to Jupiter, it probably should have a camera.  Energetic particle detectors, Magnetometers, and Auroral Mappers are great for science, but what the public is inspired by is pretty pictures of wild and distant worlds.

Juno is powered by a now familiar computer, the BAE RAD750 PowerPC radiation hardened computer.  It operates at up to 200MHz (about the processing power of a mid 1990’s Apple Computer) and includes 256MB of Flash memory and 128MB of DRAM.  It (and the other electronics) are encased in a 1cm thick titanium radiation vault.  Flying in a polar orbit around Jupiter, Juno will experience intense radiation and magnetic fields.  The probe is expected to encounter radiation levels in the order of 10Mrads+.  The vault limits this to 25krads, within what the electronics can handle.  It should be noted that a dose of 10krads is fatal in most cases.  This intense of radiation will degrade the prober, even with shielding, resulting in a mission life of only 37 orbits (a little over a year) before the probe will be gracefully crashed into Jupiter.

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Continuing our goal of having test boards available for pretty much every common architecture of the 1970’s we now have a board available for testing Signetics (and later Philips) 8-bit NMOS processor, the 2650, 2650A and 2650B.  Made on a cool black PCB they are a fairly simple system, but are capable of testing some of the special features of the 2650 as well as the added features of the 2650B (if anyone happens to locate one)

These chips did not achieve the wide microcomputer success hoped for (likely due to a lack of second sourcing) they did find their way into many industrial/embedding systems, as well as many arcade/video games (including some made by ATARI).

These boards are in stock, and ship world wide for $94.95.  Head on over to the 2650 page to grab one.

Fujitsu MB86900 – Original SPARC Processor from 1987 – 14.28MHz

Back in 1987 Fujitsu was one of the founders of the SPARC RISC architecture.  The very first SPARC processors were built by Fujitsu, and used in their servers through the 1990’s and 2000’s. SPARC processors were first used in the CM-5 Thinking Machine in 1991 using 1024 SPARC processors (later upgraded to SuperSPARCs).  Fujitsu began making supercomputers based on SPARC in 1992 with the AP1000 and its UltraSPARC based successor the AP3000.  One of their latest, the K machine, is a 705,024 core 12MW SPARC64 VIIIfx based design that ranks as #5 on the Top 500 Supercomputer list.

This is why its a surprise to many that they have announced the successor to the K Machine will be similar in topology, and will be RISC based, but will not be SPARC based, rather Fujitsu has been working with another well known RISC architecture with serious HPC aspirations, ARM.  Fujitsu has been an ARM architecture license holder for some time and the post-K machine will be based on the 64-bit ARMv8 architecture.  ARM has been working hard to make their chips appeal to the datacenter environment, with some success.  Their low power consumption makes them ideal for high density applications, which a super computer needs.  Estimated performance is 1,000 Peta FLOPS and it is due to go into service in 2020. A speed that would eclipse another recently announced RISC supercomputer….

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Azul Systems V03A0L1-Vega 3 – 54-core RISC Java Processor

Azul Systems was started in 2002 to do what anyone who has used Java wishes it to be, make it faster, and more scalable.  Azul did this using both software (optimized Java compilers/Run time environments) and hardware.  The Vega processor line was Azul’s attempt at a hardware acceleration of Java.  This wasn’t a new concept, many companies have created hardware implementations to execute Java.  Notable is the Jazelle extentions from ARM, which can directly execute Java byte-codes and Sun developed the pico.Java processor to do similar.  The Vega takes a rather different route though.  Azul found that direct execution of Java byte codes wasn’t really that important if you had very efficient JIT (Just In Time) compilation to an efficient architecture.  This allows the processor to be a bit more adaptable as you now have a layer between the hard to change hardware, and the Java feeding it.  New instructions, or work arounds/speed up become easier to implement.

The Vega 3, the last of the Vega series is a 54-core processor, each core is a classic 3-address 64-bit RISC processor with 32 registers and 16K of Instruction cache + 16K of Data cache.  The architecture is designed to be ‘Java friendly’  with fairly weak memory model for easier scaling, support for more robust garbage collection, and not a large focus on FPU performance. There is 12MB of L2 cache on chip as well (each 9-cores share 2M). The chips are fab’d by TSMC on a 65nm or 90nm process (it isn’t clear which from Azul’s documentation).  All registers and caches support ECC, and the chips themselves self-report any problems, allowing the system (which may use up to 16 chips (864 cores) to disable any misbehaving processor or memory).

Vega 3 – 54-core die. Truly massive die. Software though allows workaround for many hardware defects.

The Vega 3, and the systems it was used in, allowed Java to be scaled to much larger heap sizes (500G+) and core counts, without coherency problems.  Many institutions (especially financial) still use Java programs that were written long ago, recoding them would speed them up, but that is not practical.  The Vega3 (and other Azul products) allow old code, to be ran faster with no modifications.

Azul sold many systems running the Vega processors but eventually moved to software only solutions, that could efficiently run Java on existing x86 hardware.  The methods though are similar, just no longer the need for custom hardware to run it on.  Azul appliances can be added to any datacenter to catch and accelerate Java applications.

Azul wasn’t the first company to accelerate Java, and they certainly won’t be the last.  Java’s simplicity and platform independence will keep it around, and the ability to run decades old code fast and safely on modern hardware will continue to drive products.  Its like COBOL all over again…

National Semi SC/MP Test Board

National Semiconductor released the SC/MP (aka the SCAMP or ISP-8A-500) in 1974 as a low cost PMOS 8-bit processor.  Later the design was moved to an NMOS process resulting in higher clock speeds and simpler power supply requirements.  This version was known as the SC/MP II or the ISP-8A-600.  It was used well into the 1980’s.

This test board is designed to test with the PMOS or the NMOS versions of this chip.  It has power supplies and clocking for both the PMOS and NMOS versions and requires only the slide of a switch to change between them.

I have a couple in stock, $94.95 with FREE shipping.

More info and purchasing info on the SC/MP Test Board page.