Christoph Morlinghaus in front of the very large prints of an Intel 486DX and Motorola 68030

I recently had the pleasure of helping noted photographer Christoph Morlinghaus with a die photo project.  Christoph takes photos with a large format 8×10 film camera, and wanted to do some of processor dies, so the museum sent him off a box of chips. After a lot of work decapping and cleaning the chips, as well as finding ones with the most interesting dies, Christoph was able to take some stunning shots, no easy feat with the long exposure times required for such a camera.  Exposure times for these shots can run into the minutes, and even something as minor as a truck driving by can create enough vibration to ruin the shot.  Dies also had to be selected to show a variety of detail, colors, and be big enough to take a picture of, ideally a half inch on a side or better.  You can view the results here on Morlinghaus.com. Some very large format prints are currently on display at the Snap! Gallery in Orlando Florida as well.

Christoph did 7 total die shots of a variety of processors spanning 15 years of computing.  Dies included are: Intel 186, 486 and Pentium (P54CS), Motorola MC68020 and MC68030 as well as a Cyrix Media GXm and Cx486DX2. A 17″x22″print of each was donated to the CPU Shack, which are now framed and hanging, where they make a very nice display, as well as truly artistic pieces.

Atmel PC7410MGH450LE – Motorola Marked Package – 2003

In the 1970’s second sources were quite important in the processor industry.  They provided a stable supply of a designed in part if the primary manufacturer (which often only had a fab or 2) had problems.  They also could widen the market for the processor.  Many of these agreements were kept active for decades after, resulting in some interesting results.

Motorola licensed many of their design to SGS, which later merged with Thomson to become STMicroelectronics. though the Thomson name was still used.  Thomson license built most of Motorola’s product line, as well as many high reliability versions.  In 1999 Atmel bought Thomson-CSF Semiconductors, and continued to make Motorola products (in their Grenoble France fab), which now included Motorola’s PowerPC line as well as the 68k line of processors.  This portion of Atmel was sold to e2v (in England) in 2006, which continued to produce the Motorola (now spun off as Freescale) PowerPC line, now branded as e2V.

The packaging used by e2v (and previously Atmel) is the same as that used by Motorola/Freescale.  The packages were custom made for Motorola/Freescale by Kyocera (and others) and so often chips with both Atmel/Motorola and e2v/Freescale markings can be found.  It is this packaging that is of interest, as it shows an interesting aspect of processor design.

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Chip that come into the museum are all scanned on a Canon 5600F flatbed scanner.  It has a good (there is some better though) depth of field, and its fast.  Typically chips are scanned at 300dpi, or for small ones (or ones that have a die visible) 600dpi.  This keep the file sizes reasonable, yet still allows them to be studied in good detail on CPUShack.com as well our records.

There are on occasion chips that are VERY hard to scan, either the markings are very small, or very shallow.  This is becoming common on more modern chips, for one the chips themselves are smaller, and second, they are most often laser marked, and there isn’t enough thickness in the package (or die on some) for the Grand Canyon engraving of the 80’s.

1200 dpi dry scan

This is a Intel QG80331M500 IO Processor made by Intel in 2007.  It is the replacement for the 80960 based I/O processors, using instead a 500 MHz XScale ARM Processor core.  This scan was done at 1200 dpi, the part number is visible, barely, but the S-spec and FPO (lot code) are not.  The markings are laser etched directly onto the surface of the silicon die.  This is fairly common on this type of chip (as well as most all of Intel chipsets).  How do we improve upon this?  Bumping the resolution to 2400dpi just makes a bigger blurry picture (with more noise).  What we need is better resolution, at where the scanner works best (less noise at 1200 dpi scan).

Thankfully we can use a ‘technology’ that is very much similar to how modern processors themselves are now made.  Dumping water on the scanner, also known as immersion scanning.

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MCS-4 Test Boards

The MCS-4/40 Test boards are now back in stock and shipping this week.  Only have a few available so head on over to the MCS-4 page to order yours.

I also added a PDF of the boards schematic to make interfacing to it easier for any projects you may have in mind.

If you do have a project in mind, or already made one, post about it in the comments, we’d love to see/hear about it.

Pagetable.com has in interesting post about emulators, specifically one created in 1978 to run Intel 8080 code on a 6502.  While emulators today are fairly common, such as running Nintendo (6502) games on a PC, or In Circuit Emulators for development, an 8-bit cross architecture emulator is certainly different.  Especially since the 8080 and 6502 were so vastly differing.  Certainly a useful tool for teaching oneself a new architecture, and as they were coming out rather rapidly in the 1970’s knowing more then one was a worthy investment.

Todays equivalent perhaps would be emulating a PIC on a 8051.  Perhaps someone will give it a try?

Dawn’s mission: Ceres

Dawn was launched in 2007 by NASA/JPL and was built by Orbital Sciences becoming their first interplanetary spacecraft.  Dawns mission was to visit the two largest dwarf planets in the Asteroid belt, Vesta and Ceres.  After visiting Vesta for over a year in 2011-2012 Dawn used its ion engines to break orbit, and travel to Ceres, a journey of 2.5 years.

In the next few hours Dawn will be captured by Ceres gravity and begin orbiting it.  These protoplanets, are very interesting scientifically as they provide a look into our solar systems past.  Dawn will orbit Ceres for several years and perhaps discover what the mysterious bright spots are, among other things.  Studying a planet, even a dwarf planet, requires processing power, and for that Dawn is well equipped.

Dawn is solar powered, so power budgets are of great concern.  At 3AU (three times further from the sun then Earth) Dawns solar panels are rates at about 1300 Watts.  This has to run all the science experiments, the main computers, the comms, and most importantly the electric ion engine, which uses electricity generated from the panels to excite and eject Xenon gas at very high velocities.  Thus, power consumption is more important then raw processor power here, especially for the systems that are on most of the time.

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DEC 78032 DC333R MicroVAX II – 5MHz

DEC’s 32-bit VAX architecture saw many implementations since its introduction in 1977.  Early implementations were all multi-chip, but as technology improved the VAX architecture could be implemented (at least partially) on a single VLSI chip.  The first implementation on a single chip was the MicroVAX II released in 1985.  It contained 125,000 transistors, made on a 3 micron NMOS (DEC proprietary ‘ZMOS’) process and ran at 5MHz (200ns cycle time).

In 1987 DEC released the CVAX, the second generation VAX on VLSI.  The CVAX was made on DEC’s first CMOS process, a 2 micron design using 175,000 transistors and clocked from 10-12.5 MHz (80-10ns cycle time).  The input clock was a four-phase overlapping clock (so input frequency was 4x the cycle time, or 40-50MHz).  Performance was 2.5-3 times better then the MicroVAX II.  About half the gain was from process improvement (increased clock speed), while the rest was from architectural changes (mainly pipelining).

DEC DC580C 78034 CVAX+ 16.67MHz

As the CVAX (and its successor the CVAX+) were released the next generation was already being designed by DEC.  This was to be Rigel.  Rigel has a 6-stage pipeline, and was made on a 2 micron CMOS process and the CPU contained 320,000 transistors, 140k of which were for logic, while the remaining 180k were for memory (cache). The separate FPU chip contained an additional 135,000 transistors.  After some early teething pains on the new CMOS process, where yields were almost non-existent, the process finally was refined enough to make commercial samples by late 1988.  The target speed for Rigel was a 40ns cycle (25 MHz clock).  This would give the Rigel a 6-8x performance gain over CVAX.  2X of this was from the process shrink (and doubling of clock speed) while 3X was from the improved pipelining.  The remainder was due to increased memory performance, not the least of which was due to Rigels 2KB of on chip cache.

Rigel, however, had other plans…

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NEC SX-ACE Processor Prototype – 2013

When Vector computing is mentioned, the first company that comes to mind is Cray.  Cray was the leading designer and builder of vector supercomputers since the 1970’s.  Vector computing is a bit different then general purpose computing.  Simply put, a vector computer is designed to perform an instruction on a large set of data at the same time.  Such vector support has been added to x86 (in the form of SSE) as well as the PowerPC architecture (AltiVec) but they were not originally designed as such. Cray however, is not the only such company.  In 1983 NEC announced the SX architecture.  The SX-1/2 operated at up to 1.3 GFLOPs and supported 256MB of RAM per processor.  By 2001 with the SX-5 and SX-6 performance had increased to 8 GFLOPS and supported 8GB of RAM per CPU.  For a short while Cray themselves marketed and sold NEC SX computers.  Each of the processors, from SX-1 to the SX-9 was a single core processor, but with the SX-ACE, that changed.

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Z80 Expansion Board

Now available at The CPU Shack are the Z80 and i8085 Expansion boards for the MCS-80 test boards.  The i8085 and Z80 expansion tools allow the MCS-80 test-board to test the function of Intel 8085 (and compatible) or Z80 (and compatible) CPUs. The test tools are connected via the ZIF socket for the i8080 CPU and into the 3×16 pin header connectors of the MCS-80 test-board. There is no need to modify or replace anything on MCS-80 test-board.

This is possible because both the Z80 and i8085 CPUs are based on the Intel 8080 processor.  The 8085 is nearly the same as the 8080 from a software point of view, Intel just greatly simplified the hardware required to support it.

They are currently available for $29.95 each shipped.

TI RAY9000C-X – SBR9000 Radiation Tolerant Processor

In the previous post the TI TMS/SBP9900 was covered, as well as its successor the SBP9989.  The 9989 was to be replaced by the 9989E, a 50% shrink to 2.2u.  This was never released, but TI did continue to develop the bipolar line of the 9900s.  After canceling (or perhaps just renaming?) the 9989E/9990 TI announced the SBR9000 in 1985.  The SBR9000 was a hi-speed 9989 successor fab’d on a 2 micron I²L process and clocked at 9MHz (twice the speed of the 9989).  The change in prefix from SBP to SBR hints at another feature, while the SBP9989 was a MIL-STD-883 rated part, the   SBR9000 (and its peripherals) were designed for very high radiation tolerance.  The SBR9000 was spec’d to have a total dose tolerance of 1 MegaRad (it should be noted that around 10 krads proves fatal to the average person).

The part number of this example, RAY9000C-X is a bit mysterious but there are some strong clues as to its being a prototype of the canceled SBR9000.  First of course is the 64-pin CDIP package, conveniently having 4 ground pins marked.  Pins 1,2,27 and 28 are the ground pins on all SBP9900/9989 devices.  The SBR was to be pin compatible so has the same ground pins.  The date on the back of the RAY9000 is 8525, the SBP9900 was out of production in 1983 so that rules it out, leaving either a 9989, or the most likely, a sample of a SBR9000.  Why TI canceled the SBR9000 remains a mystery, perhaps they found the 9989 to be adequate for their customers needs, as it continued to be produced into the 1990’s.