Comet 67P/Churyumov–Gerasimenko – Soon to have a pair of Harris RTX2010 Processors

In less then an hour (11/12/2014 @ approx 0835 GMT) 511,000,000 km from Earth the Philae lander of the Rosetta mission will detach and begin its decent to a comets surface.  The orbiter is powered by a 1750A processor by Dynex (as we previously discussed).  The lander is powered by two 8MHz Harris RTX2010 16-bit stack processors, again a design dating back to the 1980’s.  These are used by the Philae CDMS (COmmand and Data Management System) to control all aspects of the lander.

All lander functions have to be pre programmed and executed by the CDMS with absolute fault tolerance as communications to Earth take over 28 minutes one way.  The pair of RTX2010s run in a hot redundant set up, where one board (Data Processing Unit) runs as the primary, while the second monitors it, ready to take over if any anomaly is detected.  The backup has been well tested as on each power cycle of Philae the backup computer has started, then handed control over to the primary.  This technically is an anomaly, as the CDMS was not programmed to do so, but due to some unknown cause it is working in such a state.  The fault tolerant programming handles such a situation gracefully and it will have no effect on Philae’s mission.

Why was the RTX2010 chosen?  Simply put the RTX2010 is the lowest power budget processor available that is radiation hardened, and powerful enough to handle the complex landing procedure.  Philae runs on batteries for the first phase of its mission (later it will switch to solar/back up batteries) so the power budget is critical.  The RTX2010 is a Forth based stack processor which allows for very efficient coding, again useful for a low power budget.

Eight of the instruments are also powered by a RTX2010s, making 10 total (running at between 8-10MHz).  The lander also includes an Analog Devices ADSP-21020 and a pair of 80C3x microcontrollers as well as multiple FPGAs.

Real3D VM21113C1 Prototype (likely a Pro/1000)

Much of consumer tech starts life in the labs of defense companies.  The reasons of course are simple, defense projects demand high tech, and are paid high prices by their respective governments.  Usually this tech is eventually spun off or licensed to consumer companies.  Occasionally, however, a defense company will commercialize a product on their own.  Thus was the case of Real3D.

Real3D has its roots in GE Aerospace.  GE needed to make simulators, with graphics good enough to be useful for training for a variety of systems.  Their first system was a docking simulator for the Apollo Project in the 1960’s.  By the 1980’s the technology had evolved into graphics systems for other  simulators, notably the M1 Tank.  This simulator used texture mapping graphics, which was in the world of sprites commonly used on PC’s was rather high tech. In 1992 GE sold the GE Aerospace division to Martin-Marietta who then merged with Lockheed.  Lockheed Martin wanted to commercialize the graphics work GE Aerospace has developed and thus formed Real3D Inc.  in 1995. Real3D’s first commercial success was the graphics work on the Sega Model 2 (Real3D/100) and 3 (Pro-1000) arcade systems.  Real3D also began working with SGI and Intel on a PC based graphic solution to take advantage of the new AGP bus.  This was known as the Starfighter, and later as the rather infamous Intel i740, its performance was not particularly good, but it was what Intel wanted for their entry into the value graphics market.  Real3D also had the Pro-1000 whose performance was much better but it never made it out of the development stage.

In 1999 Lockheed closed Real3D and sold its assets (mainly IP)  to Intel.  The i740 was withdrawn from the market in 1999 as well, but its technology, and that of Real3D continued to be used by Intel in their integrated graphics chipsets (notably the i810 and i815), surviving still to this day.  While no competitor to AMD/Nvidia Graphics it still is enough for most computing.

SGS-Ates M380B1 – 1977

In the 1970’s the computer age was booming.  New processor designs were being pushed out by the month, and computers to use them were being designed and outdated just as fast.  Not all markets were growing as fast as the American market, or could support the newest, most complex, and expensive designs.  Thus, it was common for semiconductor companies to design chips specifically for these markets.  Europe was considered one of these markets, where simpler more affordable devices were easier to sell, thus CPUs were made specifically for the European market.  Many of these designs are still nearly impossible to find outside of Europe.

General Instruments was one such company.  Their premier processor, the CP1600, was a 16-bit deign based on the PDP-11.  It was one of the first NMOS 16-bit processors (along with the TI9900) and was released in 1975.  GI also had the PIC line of 8-bit MCUs for control oriented tasks, which is still in production today.  GI wanted a design for the European market so in 1976 released the LP8000, LP for Logic Processor.  The LP8000 was a 3-chip simple processor and cost a mere $10.  It could execute 48 instructions (including ADD, but subtraction was not supported directly) at a clock speed of 800 kHz and was made on a PMOS process. The chipset consisted of the LP8000 processor which contained the ALU and 48 8-bit registers as well as the accumulator a 6-bit address bus and 8-bit of I/O.  Combining the 6-bit address and 8-bit I/O busses allowed the LP8000 to directly address 16K of memory.  The 11-bit Program Counter was contained off chip, on the LP6000 which also contained an additional 16 lines of I/O and 1K of ROM for program storage.  Clock generation was provided by the LP1030 and memory expansion was handled by the LP1000 (which also includes a 11-bit PC for interfacing up to 2K of memory) while the LP1010 handled I/O expansion.  In order to be successful in Europe GI needed to find a European partner who could make, market and sell the design.

GI LP8000

That partner ended up being SGS-Ates of Italy (which later would become ST Microelectronics).  SGS-Ates second sourced the LP8000 as the M38 (or M380) series.  The M380 was the processor element, while the M382 was the 1K ROM equivalent of the LP6000.  In addition SGS-Ates made the M381 which had 18 bytes of RAM and 768 bytes of ROM as well as the PC.  Like the LP8000 the M380 drew about 1 Watt of power and required a +5V and -12V supply (or a -5V and -17V).  The M380 was rather short lived as SGS-Ates soon licensed the Zilog Z80 which was a much more powerful, yet still inexpensive, design.  When SGS-Ates purchased Mostek from United Technologies they added yet another 8-bit design, the F8, which Mostek had licensed from Fairchild.  These processors quickly replaced the M380/LP8000 and with no market, it faded into obscurity.

Intel A80501-60 SX753 – Early 1993 containing the FDIV bug

In 1994 Intel had a bit of an issue.  The newly released Pentium processor, replacement for the now 5 year old i486 had a bit of a problem, it couldn’t properly compute floating point division in some cases.  The FDIV instructions on the Pentium used a lookup table (Programmable Logic Array) to speed calculation.  This PLA had 1066 entries, which were mostly correct except 5 out of the 1066 did not get written to the PLA due to a programming error, so any calculation that hit one of those 5 cells, would result in an erroneous result.  A fairly significant error but not at all uncommon, bugs in processors are fairly common.  They are found, documented as errata, and if serious enough, and practical, fixed in the next silicon revision.

What made the FDIV infamous was, in the terms of the 21st century, it went viral.  The media, who really had little understanding of such things, caught wind and reported it as if it was the end of computing.  Intel was forced to enact a lifetime replacement program for effected chips.  Now the FDIV bug is the stuff of computer history, a lesson in bad PR more then bad silicon.

Current Intel processors also suffer from bad math, though in this case its the FSIN (and FCOS) instructions.  these instructions calculate the sine of float point numbers.  The big problem here is Intel’s documentation says the instruction is nearly perfect over a VERY wide range of inputs.  It turns out, according to extensive research by Bruce Dawson, of Google, to be very inaccurate, and not just for a limited set of inputs.

Interestingly the root of the cause is another look-up table, in this case the hard coded value of pi, which Intel, for whatever reason, limited to just 66-bits. a value much too inaccurate for an 80-bit FPU.

Zilog Z80A CPU -1978

Ken Shirriff has an excellent write up about the Zilog Z80 and why its pin-out, specifically the Data lines, is a bit convoluted.  Rather then being in order (such as D0-D7) the original Z80 is D4,D3.D5,D6,D2,D7,D0,D.  Its functional but its not pretty and can lead to some interesting PCB layout issues.  Ken uses data/imaging from the Visual6502 project to look at the on die reasons for this.  Essentially it came down to saving die space. there literally was not enough room to route the data connections within the confines of the die size.  Keeping the die size small allowed Zilog, and its many second sources), to keep prices down.  In the early days Zilog contracted Mostek to make much of their processors, so die size and the associated cost were a big issue.

Anandtech and Chipworks deconstructed an Apple A8 processor, the hear of the new iPhone 6.  By their analysis it is not a radical departure from the A7.  It includes a slightly upgrade, but still quad-core, GPU, and an enhanced dual core ARM processor.  The focus here is clearly on battery performance rather then sheer speed.  Perhaps most interesting is the move from Samsung’s 28nm process to TSMC’s 20nm process (Being made by TSMC will hopefully put to rest the rumors of an Apple/Intel tie up once and for all.).  This results in lower power, a smaller die area, and, assuming yields are on par, a lower cost per chip.  Clock speed appears to be close to the same as the A7 at around 1.3GHz, with most performance improvements being architectural. It would appear to be the smallest improvement in the Apple A series, certainly since the A4->A5.

Considering the incremental improvement from the A7, one can only imagine what Apple has in mind for the A9 which is no doubt well under development.

National Semiconductor MM5782N – 400KHz 1976

In August we detailed the COP2404 and the COP400 line of 4-bit microcomputers by National Semiconductor.  This NMOS design originated in 1977 and was made for over 30 years.  It, however, was not the the first COP line of National Semiconductor.  In fact the COP400 family was referred to as the COPS II for a brief period in the 1970’s.  If the COP400 was the second in line then what was the ORIGINAL COP microcomputer?

That would be the COPS I of course, better known as the MM5781/2 and its derivatives, the MM5799, MM57140 and MM57152.  These microcomputers were released in 1976 and were made on a volume PMOS process.  They were designed to be inexpensive and simple to use.  The design of the 5781/2 actually started with the MM5734 which was a single chip accumulating calculator chip.  The differences are not as big as one may think.  A multi-function calculator with memory needs an ALU, registers, ann accumulator and instruction decoding, as well as very limited memory and fairly extensive I/O (to run the display and read inputs from the keyboard).  National saw this as an opportunity to capture a bit of the low-end market.  They already had the IMP-16 for their high end, the SC/MP for the mid range, as well as second sourced Intel MCS-4 and MCS-80.  What they lacked was something to compete with the likes of the WD1872 and the TI TMS1000 series as well as the rise of the Japanese 4-bit solutions from NEC, Toshiba and Sanyo.

The 5781/2 was a 2 chip solution, together they formed a microcomputer.  The 5781 contained the program ROM (2048 x 8 bits), as well as the program counter and some control logic.  The 5782 was contained the full ALU, the accumulator, the instruction decoder, and 160×4 bits of RAM.  It could execute 33 different instructions.  Clock speed was 70-400KHz and was provided by an off-chip oscillator.

National Semiconductor MM5799 – Single chip COPs

National combined the 5781/2 into a single 28 pin chip called the MM5799.  It contained all the logic of the 5781/2 but with a smaller amount of RAM (96 x 4 bits) and ROM (1500 x 8 bits). Clock speed remained the same but the instruction set was expanded slightly to 41 instructions.  Two other versions were also made that had more extensive I/O.  The MM57140 which had build in LED drivers, and the MM57152 which was the same, but had built in fluorescent display drivers (this was the 1970’s after all). The ‘140 and ‘152 had 36 instructions 55 x 4 bits of RAM and 630 x 8 bits of ROM. Maximum clock speed was also reduced to 280KHz.

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MasPar PE3232 – 32 12.5MHz 32 bit Processing Elements – 1992

In the 1980’s DEC researchers were designing a supercomputer based on the Goodyear MPP from 1983.  Jeff Kalb was in charge of the division of DEC involved in this work.  The original Goodyear MPP wa based on a 1-bit processor element (PE).  DEC increased that to a 4-bit PE as well as increased the connectivity between PE’s.  When DEC decided to not commercialize the supercomputer design Kalb left (with DEC’s blessing) to start a company of his own that would.  Thus the creation of MasPar in 1987.

MasPar derives its name from the product it sought to create, a Massively Parallel supercomputer.  These type of computers, also referred to as vector processors are SIMD machines, Single Instruction, Multiple Data.  They perform the same operation on a very large set of data.  SIMD instructions are now found on most all desktop processors, where they can greatly speed up processing of multimedia.  In the late 1980’s there was several companies making such MPP computers.  Perhaps the most famous was Cray, but there was also Thinking Machine’s Connection Machine, Intel’s Paragon (i860 based), nCUBE’s hypercube, Meiko Scientific’s CS-1 (Transputer based) and several others.  Such systems cost from upwards of $100,000 each so sales were not vast, typically companies sold a few hundred to a few thousand systems.

MasPar’s first design, the MP-1 was based directly on the research done at DEC.  Each processing element contained a 4-bit ALU, a 1-bit logic unit, a 64/16 (mantissa/exponent) unit for handling floating point.  Each PE also had 48 32-bit registers.  There were designed as a 32-bit RISC processor, which means, that with the 4-bit ALU, any ALU operation would take at least 8 cycles.  This was considered acceptable in a MPP type system.  Each custom VLSI CMOS MP-1 chip contained 32 individual PE’s.  They were made on a 1.6u process and contained 400,000 transistors.  Clock speed was a fairly low 12.5MHz but this allowed the chips to be air cooled with no special cooling systems.   They were packaged in an inexpensive 208 PQFP, nothing special needed due to the low heat dissipation.  A 1024 PE board (32 chips) dissipated only 50 Watts, and an entire 16k processor system dissipated less than 1,000 watts.

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Cx486SLC/e-33MP Based Improve Technologies Make-It 386 for a 286

Improve Technologies (IT) was a company that existed from 1991-1997.  They were one of the many (to include Cyrix, Evergreen, PNY, Gainbery, etc) that made processors for upgrading 286, 386 and 486 computers.  Processor upgrades are no longer commonplace, becoming nearly non-existent (except for such things as 771 to 775 adapters).  Today computer hardware has become so inexpensive that upgrading more often just consists of purchasing a whole new computer, or at least new motherboard, RAM, and CPU, all at a price of a few hundred dollars.

In the early to mid-90;s however, a computer system cost 2-$3000, so replacing it every few years was not financially viable for many people.  Thus processor upgrades, they were designed to replace a CPU with the next generation CPU (with some limitations) at a price of a few hundred dollars.

In 1976 TranEra was founded in Utah. TransEra is an engineering solutions company, they are built on seeing a technological problem, and engineering a solution, whatever that may be.  They began by making add-on for Tektronix test gear and HP-IB interface equipment.  In 1988 they released HTBasic, a BASIC programming language (based on HP’s Rocky Mountain BASIC) for PC’s.  This is what TransEra became perhaps best known for, as they continue to develop and sell HTBasic.  It was TransEra who developed the Improve Technologies line of upgrades.  They saw a problem, and engineered a solution.

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National Semiconductor COP2404N – Dual core processor

National Semiconductor introduced the COPS series of 4-bit processors in 1977.  COPS came from National’s calculator line of chips, and for a short time were known as Calculator Oriented Processors, however this was rapidly changed to Control Oriented Processor System (COPS).  These 4-bit microcontrollers, as their name suggests, were for controlling various consumer devices.  They were used in all sorts of devices from game consoles, to dishwashers.  In the early 1980s National began producing them in CMOS versions, and in 1988 they extended the line to 8-bit (the COP8 family).

COP2404 Block Diagram – 2 Cores with shared memory. – Click to enlarge

In 1981 the COP2404 (and 2440) were announced, with availability beginning in 1982.  The COP2404 was on the top end of the COPS line, it was found that some real time control operations were better served by 2 microcontrollers, so why not design 2 into one.  The 2404 is a dual core processor, with two complete COPS404 cores on one die, sharing I/O and RAM. (The 2440 also included ROM).  True to multi-core form, the memory was shared, meaning the processors could work independently or pass data to each other, including task handoffs if the programmer so desired.  This wasn’t implemented in hardware, but it wasn’t forbidden either, meaning a programmer could do some pretty complicated task management with the dual CPU cores.

The 2404 was packed in a 48 pin PDIP, and was designed as a development device for use with external program memory (EPROM typically).  Production devices were the 2440 (40 pin) 2441 (28 pin) and 2442 (24 pin) which all had 2K of ROM on die.  All included 160×4 bits of RAM and had an instruction cycle of 4usec (using a 4MHz clock, as each instruction took 16 cycles).  They were manufactured on a 3-micron NMOS process (originally, likely shrunk over time).

As technology progressed it became easier to handle multiple real time tasks with a single, faster controller, with good hardware interrupt handling, but for a time, their was a dual-core processor.  The COPS series continued to be sold by National until 2011, when they were bought by Texas Instruments.  While no longer actively marketed, several members of the COP8 line are still being sold.