Total CPU's: 20,000+
Total Manufacturers: 150+
Total EPROM's: 2000+
Here is a very unusual Engineering Sample from Intel. These were manufactured in 1996 with a 1994 copyright date. They are slightly smaller then a Socket 5 Pentium and are a 325 pin SPGA package.
Intel KJ8TSMR00-BA – Engineering Sample
Marked KJ8TSMR00-BA the best guess so far is a early P6 (Pentium Pro) core, without the L2 cache. If you have any ideas, feel free to post in the comments.
Xionics XipChip1
It was the late 90s and high integration was the name of the game. Xionics (based in Burlington, Mass) and IBM set out to create an intelligent peripheral controller meant to replace logic/ASICs in printers, copiers, and other imaging products with something more useful. Xionics was originally founded in 1978 in the U.K. and in the 1980s began making document imaging products.
The XipChip1 is what they came up with. It is a PowerPC 401 core, running at 40MHz with 2KB I Cache + 1KB D Cache made on a 0.36u 4-Layer CMOS process at IBMs plant in Bromont Canada. They included a JPEG engine, DMA controller, Raster Graphics Engine, and a 240MHz RAMBUS controller (hey it was the 90s, RAMBUS was all the rage). Xionics sold their technology to a number of printer companies (Ricoh, Panasonic, Xerox, HP and many others) and their software was widely adopted. By 1999 Xionics was bought out by Oak Technology which was acquired by Zoran in 2003.
Soviet Vostok K573RF23 – 2kx4 – 1984
This EPROM, made in November of 1984 at the Soviet Vostok factory in Novosibirsk started life as a 2716 2kx8 EPROM. A Soviet 2716 would be marked as 573RF2, whereas this particular example is marked 573RF23. The die is a 2716 that was found to be defective, and thus converted to a 2kx4 EPROM, this is denoted by the adding of the 3 to the part number. This certainly was not an uncommon procedure, even Intel regularly sold 2708 EPROMs as 2704s, whether to use a die with an imperfection, or to simply meet demand.
There are two other interesting markings on this particular EPROM. First is the CCCP logo, this is the State Quality Mark of the USSR. This quality mark was used to signify that products met the following conditions:
Meeting these conditions allowed the factory to sell such devices at a 10% premium. So not only was Vostok able to pass a defective part as a quality part, they were able to do so and make a bit extra revenue. Thats something Intel would be quite envious of.
Some references show that 573RF23 as being the equivalent of a 2758 EPROM (5V 2708). This is in fact incorrect. A 2716 converted to a 2708 is done so simply by removing a single address line (going from 11 to 10) The 573RF23 retains 11 address lines, but it removes 4 data lines, thus making it 2kx4, same number of address locations, but each locations contains only 4 bits, vs 8 bits. Rewiring address lines likely did not allow for a working EPROM due to where the defect was, thus cutting the word size down. The first condition of the State Quality Mark is that said EPROM should meet or exceed the best international analog. Intel did not make a 2kx4 EPROM, the closest western analog would be the Harris/Intersil IM6657, though it was made in CMOS, vs the 573RF23s NMOS, so one could say that it was easy to beat a analog that did not exist.
The other mark on this EPROM is OTK, which literally means “Technical Control Department,” in others words this part passed the quality control dept, hopefully after it was converted to the lower capacity device, and them marked with the State Quality Mark. Perhaps it was the best NMOS 2kx4 EPROM the world was to see, certainly it came in a beautiful package.
HP C5061-3012 – 16 Bit – 4 MHz – 1984
In last months article on HP’s 16 bit processors we mentioned it was made in a reduced version (on an enhanced NMOS III process). This CPU was known as the C5061-3012. It contains only a BPC (Binary Processor Chip) and no EMC or IOC. It was meant for simpler designs, such as a tape controller, but also in some other HP test equipment. While a simpler implementation, it would seem that HP chose to continue the use of rather beautiful, and highly delicate packaging. This example was made in 1984, a time when most other ICs were grey ceramic or plastic, not a white/gold ceramic package.
This was meant to mounted to a heatsink, which dissipated the heat as well as protected the wafer this ceramic (the package, other than where the die is, is less than 1mm thick)
1985 production 68020 ‘XC’ denotes a not fully qualified device.
In 1979 Motorola wow’d the world with the introduction of the MC68000 MACSS (Motorola Advanced Computer System on Silicon). One of the first single chip 32-bit processors. In 1982 the design was upgraded and revised, and released as the 68010. Performance wasn’t that much better then the original 68k so it saw much smaller adoption.
In 1984 Motorola continued the 68k line with the 68020. Speed was greatly improved, up to 33MHz. It was originally made on a 2 micron HCMOS process, allowing the design to use 200,000 transistors and integrate additional addressing modes, co-processor support, and multi-processor support.
The Swedish Computer archeology blog Ehliar has a nice article and die shots on its architecture and design. Check it out.
HP D5061-3001 – 10MHz 24,000 Transistors
40+ Years after computer processors began to be made, there are several that stick in peoples minds as ‘the greats’ as being somehow more important then others. Processors such as the Intel 4004, the MOS 6502 of Apple fame, and the Motorola 6800 have taken histories podium as the most important.
The truth, however, is a bit different, yet no less exciting. There are those processors that at their time, were vastly ahead of their time, such technological marvels that they continued to be competitive for a decade, impressive today, nearly unheard of in the 1970’s. Some of these processors never saw wide use in PCs, such as the 1802 or SMS300 yet were remarkable. Still others were designed not to be mass market, or to be licensed but to satisfy a company’s internal needs for a processor to power their equipment. These in house designs were every bit as impressive as the competition but since they were used by their creators alone, they faded into obscurity. One such example was the Bell Labs BELLMAC-8, designed by, and for Western Electric. They were not alone however…
IBM z800 MCM
Mainframes are the workhorses of the computing industry. They process transactions for about every industry, and handle the brunt of the economy. Their MTBF (Mean Time Between Failures) is measured in decades (typically 20-50 years). A comparison to a home computer is hard to make, they are in an entirely different league, playing an entirely different game.
Data Intense vs. CPU Intense
Mainframe processors such as these work in what is referred to as ‘Data Intensive’ computing environments. This is different from multi-cored processing that focuses on ‘CPU Intensive’ computing. CPU intense has a relatively small data set, but most perform a lot of work on that set of data, or do the same instruction on a set of data (such as graphics). CPU Intense processing can often be sped up with the addition of more processing cores. Data Intense processing does not see as much benefit from adding cores. Its biggest bottleneck is accessing the data, thus the System z tends to have VERY large caches, and very high bandwidth memory. They typically operate on transactional type data, where the processing has to operate in a certain order (A has to be done before B which has to finish before C etc).
IBM was one of the first, and continues to be one of the largest suppliers of such systems. Starting with the System/360 introduced in 1964 to the zSeries today. The zSeries was first launched in 2000 with the z900, a significant upgrade from the System/390. Data addressing was moved to 64-bits (from 31 bits) yet backwards compatibility (all the way back to the 360) is maintained. The z900 ran at 775MHz and was built with a 35 die MCM containing 20 Processing Units (PUs) and 32MB of L2 Cache.
ARM 701 mis-print on the left
We recently received several Remote Server management cards, powered by the Agilent (spun off of HP in 1999) N2530 SoC. This SoC provides the processing for remotely administering, and managing servers. At its hearts is an ARM processor running at 33MHz. Proudly marked on the chip, is ‘ARM 701 POWERED.’ There is one problem, there never was an ARM701 processor core. The N2530 is in fact powered by an ARM710. A typo was made when marked the Rev D chips, and later fixed on the Revision E. I have not yet received an example of a Rev C (or earlier) to see if they too have this error, but E and later certainly did not. The Agilent N2530 was used for many years in the early 2000’s on cards by Dell, Fujitsu, and IBM (and likely others). Essentially forming a computer within a computer, these cards often had their own graphics support (ATI Mobility Radeon, among others) as well as support for CD-ROMs, hard drives, LAN (for access) and everything else you would find in a stand alone computer. Typically they could remote start, reboot, and power down servers, all over a network connection.
Bloomberg Business Week recently published an interesting article on ARM’s rise to power in the processing world. There first major design ‘win’ was a failed product known as the Apple Newton, yet they would go on to become a powerhouse that is no challenging Intel.
In ARM’s formative years, the 1990’s, the most popular RISC processor was the MIPS architecture, which powered high end computers by SGI, while Intel made super computers (the Paragon) based on another RISC design, the i860. Now, nearly 2 decades later, after Intel abandoned their foray into the ARM architecture (StrongARM and X-Scale) RISC is again challenging Intel in the server market, this time, led by ARM.
MIPS, now owned by Imagination, is again turning out new IP cores to compete with ARM, and other embedded cores. Their Warrior class processors are already providing 64-bit embedded processing power, though with a lot less press that the likes of Apple’s A7.
IBM POWER5+ QCM – 4 dies, 8 cores, and 72MB of L3 Cache
When the POWER5 processor was released in 2004 it was made in two versions, a DCM (Dual Chip Module) containing a POWER5 die and its 36MB L3 cache die, as well as a MCM containing 4 POWER5 die and 4 L3 cache dies totaling 144MB. The POWER5 is a dual core processor, thus the DCM was a dual core, and the MCM an 8 core processor. The POWER5 contains 276 million transistors and was made on a 130nm CMOS9S process.
In 2005 IBM shrank the POWER5 onto a 90nm CMOS10S manufacturing process resulting in the POWER5+. This allowed speeds to increase to 2.3GHz from the previous max of 1.9GHz. The main benefit from the process shrink was less power draw, and thus less heat. This allowed IBM to make the POWER5+ in a QCM (Quad Chip Module) as well as the previous form factors. The QCM ran at up to 1.8GHz and contained a pair of POWER5+ dies and 72MB of L3 Cache.
The POWER5+ was more then a die shrink, IBM reworked much of the POWER5 to improve performance, adding new floating point instructions, doubling the TLB size, improved SMP support, and an enhanced memory controller to mention just a few.
The result? A much improved processor and a very fine looking QCM.
