Before we get into the fascinating story of the Soviet (specifically the Angstrem) Z80 clone it’s good to understand a bit about the IC industry in the USSR.  There were many state run institutions within the USSR that were tasked with making IC’s.  These included analogs of various western parts, some with additional enhancements, as well as domestically designed parts.  In some ways these institutions competed, it was a matter of pride, and funding to come out with new and better designs, all within the confines of the Soviet system.  There were also the various Warsaw Pact countries (Bulgaria, Czechoslovakia, East Germany, Hungary, Poland and Romania), that were aligned with the USSR but not part of it.  These countries had their own IC production, outside of the auspices and direction of the USSR.  They mainly supplied their own local markets (or within other Warsaw Pact countries) but also on occasion provided ICs to the USSR proper, though one would assume an assortment of bureaucratic paperwork was needed for such transfers.

This resulted in some countries developing similar devices, at rather different times, or different countries focusing on different designs.  East Germany was all in on the Z80, Romania, Poland and Czechoslovakia made clones of the 8080, Bulgaria, the 6800 and 6502. They were though, seperate from the USSR’s own institutional system, so while East Germany had a working Z80 in the early 1980’s the USSR did not.  It is this distinction we will focus on today

This article is largely from guest author Vladimir Yakovlev, translated from Russian, and edited/expanded by me.

By the end of the 80s – beginning of the 90s, clones of the British Sinclair ZX Spectrum computer, a simple, cheap computer with a huge library of games originally released in 1982, were being distributed in the USSR. The “strapping” of the central processor instead of the original ULA microcircuit was done on small logic microcircuits of the 555 (74LS) series and the like, but the Z80 itself had to be bought from abroad. Naturally, the thought arose, to start making the processor yourself. After all, the processor itself, developed in 1976 for the microelectronic industry, was not too complicated.

In 1990, the development of an analogue of the Z80 was organized in Zelenograd near Moscow at the Scientific Research Institute of Precise Technology (NIITT) and the “Angstrem” plant. Initially, Zelenograd was conceived as a center of the textile industry, but was later reoriented to the development of electronics and microelectronics by Nikita Kruschev after he visited Silicon Valley (California, USA) in 1959. To this day, Zelenograd has retained the status of a scientific center and the informal name “Russian Silicon Valley”.

The chief designer was appointed Yuri Otrokhov, who had previously led similar developments. Otrokhov, who served as a tanker in his youth (military service being mandatory in the USSR), called the project the T34 microprocessor.

Otrokhov: “T-34VM1 is the internal designation of the KR1858VM1 processor, assigned by me at the stage of development and production in honor of my first tank, on which I learned to drive.”

Here is one of the versions of the creation of the clone, outlined by one of the employees of NIITT at that time, Boris Malashevich [1]:

“Otrokhov, like his colleagues in the department, knew how to develop original microprocessors, but they had not yet had to reproduce analogs. Therefore, the developers included specialists from NIITT divisions who are able to restore the electrical circuit of the IC according to its topology. For 9 months after four iterations, they managed to make an NMOS microprocessor T34VM1 (KM1858VM1, KR1858VM1) – a complete analogue of the Z80A microprocessor, to be made using a 2-micron technology” (The original Zilog version was on a 4 micron process).

While Otrokhov and his team worked at Angstrem to make a NMOS Z80, a similar team was working at ‘Transistor’ in Minsk Belarus to make a CMOS version, later known as the KR1858VM3.

Due to the incredible popularity and demand for the Z80, many analogue manufacturers worked without a license, so in total less than half of all Z-80 produced were licensed products from Zilog or its official partners (SGS, Mostek, etc).

From an interview with the creators of the Z80 [2]:

Faggin: Yes, we were concerned about others copying the Z80. So I was trying to figure what we could
do that that would be effective, and that’s when I came across an idea that if we use the depletion load
the mask that doesn’t leave any trace, then I could create depletion load devices that look like
enhancement mode devices. And by doing that we could trick the customer into believing that a certain
logic was implemented, when it was not. Then I told Shima, “Shima, this is the idea how to implement
traps. Put traps, you know, figure out how to do the worst possible traps that you can imagine,” and then
Shima with his mind, that was steel mind, was able to actually figure out a bunch of traps that he could
talk about.
Shima: I didn’t count [on] talking about that mostly. I placed six traps for stopping the copy of the layout
by the copy maker. And one transistor was added to existing enhancement transistors. And I added a
transistor looks like an enhancement transistor. But if transistors are set to be always on state by the ion
implantations, it has a drastic effect on very much. I heard from NEC later the copy maker delayed the
announcement of Z80 compatible product for about six months. That is what I got from NEC. And finally
a total transistor of Z80 became 8,200 while a total of transistor of 8080 was 4,800.

In the course of the design, due to the fact that the development team had specialists in both the creation of new ICs and the reproduction of analogs, Zilog’s tricks aimed at copy protection were identified and decrypted. For example, the topologist saw the 3-Input-NAND Gate element, but this element worked as 2-Input-NAND Gate. The topology and layout of the resulting clone was different, but the functionality did not differ from the original. At first, it was possible to identify such traps, making sure that the circuit was inoperable, only by examining the circuit elements inside the die using probe analyzers. But, having understood the principle of constructing traps, a mechanism for their detection was also developed. As a result, it was possible to make a full-fledged analog of the Z80, although the electrical circuit and topology of the T34MV1 had some differences.

The German Connection

Read More »

In sports, particularly Baseball, its often said that the longer a record is to say, they less impressive it is.  ‘Most Home Runs Ever’ is much more of an impressive record then ‘Most Home runs in the 7th inning against a left handed pitcher with a runner on 3rd’  Both are of course records, the first, many may even know the answer (Barry Bonds), the second? I’m sure someone can look it up but I have no idea.

So when I got this interesting commemorative AMD Opteron Sample it seems fitting to break down the record engraved on it ‘Shanghai – World’s 1st 45nm Monolithic Quad Core x86 CPU – October, 2008’  That seems impressive, and the reality is that it was (and is) and its a testament to the very hard work the design team, whose names are engraved for perpetuity on the chip, put into it.  The Shanghai was a third gen Opteron that followed the very troubled Barcelona, so it was really a make or break design for AMD.

Intel Core 2 Quad Q9100 QAVK Engineering Sample – Dual 45nm dies – Mid 2008

The most impressive aspect of the record is ‘First monolithic quad core x86 CPU.’  This was putting 4 x86 cores on a single die. Now Shanghai wasn’t the first to do this, as Barcelona had done so previously, thus the addition of ’45nm’ to the record.  Barcelona was made on a 65nm process whereas Shanghai shrank that to 45nm.  At the time Intel had the Quad-Core Clovertown Xeons (65nm) and had (in 2007) just released the Harpertown/Yorkfield Quad-Cores made on a new 45nm process.  All of these used two dual core dies in a single package. Intel was able to catch up later with the Nehalem based processors in 2009.

Was there other single die Quad-cores at the time?  What if we look outside of the realm of x86?  In 2008 IBM released the z10 quadcore processor, it was a single die, running at up to 4.4GHz (!) but it was made on a 65nm process.  Likewise, the UltraSPARC T2 was a 8-core CPU from 2007 but again, only on a 65nm process.  Freescale released the 45nm quadcore, single die P3 series P2040 PowerPC processors, but in 2010.  MIPS had the quadcore 1004K in 2008 but only on 65nm. So it seems AMD may have had a better record then they thought.

What if we stretch what we call a processor? There were at the time some fairly simple large multicores like the Tilera TILE64 (64-basic 32-bit cores) made on 45nm process, but they are less of a general purpose CPU.  Perhaps the closest is the Sony CELL Processor in the Playstation 3, which IBM was moving to 45nm in 2008 and had 1x PowerPC core + 7 SPEs. Perhaps AMD could have made a claim to the first 45nm single die CPU ever, even including non-x86 chips.

SEMICON WEST 1996 PLCC68 Memorabilia

In 1970 an industry group was started called SEMI (Semiconductor Equipment and Materials International).  They were formed to represent, as the name implies, all the various people/companies involved in making semiconductors.  This wasn’t so much the Intel’s and AMD’s but the companies that made the equipment, chemicals, and even software they used to actually design, fab, package and test chips.

In 1971 they had their first tradeshow, SEMICON WEST, at San Mateo Fairground, California.  They continue to have events around the world, SEMICON WEST is now in San Francisco (and there was a corresponding SEMICON EAST that started in 1973 in New York, but no longer exists).

SEMI not only provides an avenue for vendors and technology to be showcased, but they also work to put forth standards in industry, as well as education.  It was SEMI in the 1970’s who worked to develop standard wafer sizes, can you imagine if there was no standard sizes for such a principal component? Madness!

Lack of molded markings (usually date/country/lot would be included) suggest this was made specific for the conference.

These conferences have seminars on such compelling topics as ‘Chemical Mechanical Polishing’ and ‘Photosensitive Benzocyclobutene for Stress-Buffer and Passivation Applications.’  Today they also include vendors and information on hiring, and personnel management in the semiconductor industry, as well as safety, environmental, and education.  Certainly not as flashy as CeBIT or COMDEX, but perhaps equally if not more important.

The pictured chip was given away as swag during SEMI/WEST 1996.  Its a pretty typical PLCC68 package with the logo from that years conference.  On the back there is a complete lack of markings (even in the mold) suggesting this may have been a run specifically made for the conference, probably by a packaging vendor.

Intel SSQ22667-001 SQ80C186-12 – Space Rated CMOS 80186

Recently some interesting CPUs showed up on eBay and other IC selling sites.  They were marked SSQ22667-001 and made by Intel.  Some were conveniently also labeled SQ80C186-12.  Packaged in a 68-pin CQFP package, they typically would be labeled as a MQ80C186 (Military CMOS 186 running at 12MHz) but these were as ‘SQ’ prefix, and had the weird SSQ22667-001 part # on them as well. Others in the same package were marked SSQ22668 and 22669. So what was special about these CPUs? Was this some random House # for an OEM?  Nope, these were made for NASA, specifically to conform with MIL-STD-975.  To learn a bit more about how these MIL-STD’s work, lets take a journey back to the 1960’s (everyone knows hat was a fun time)

Back in the 1960’s integrated circuits were getting to be more standard, and more available. Many companies were making many different types (generally simple logic at the time, but that was changing fast).  The US Military was, of course, an early user of integrated circuits, as they could afford them, and IC’s allowed for some cutting edge technology.   To make purchasing and stocking such components easier, the military, as they usually do, decided there needed to be some standards, and ICs for the military, should be available in higher standards

Intel MC1702A/B – MIL-STD-883 Class B – 1976

then those destined for your microwave oven or digital alarm clock.  Thus in May of 1968 the MIL-STD-883 was released.  This was (and continues to be, its on Rev L now) a standard created on Test methods and procedures for ICs, any IC’s.  It provides such things as inspection methods, burn-in methods, lot sampling, and a whole host of other ways to test and inspect IC’s.  As the years went by, different Classes of testing were added.  A computer chip the captains coffee pot did not need the same testing as a computer chip destined for a nuclear submarine, or one for use in Space.  Several classes were then created for space, S, V, Q and B, varying in the degree of testing needed.  Obviously a vehicle designed to take people to space should use higher quality parts then one launching unmanned missions.

As IC’s continued to be developed, and many devices became ‘standard’ like various RTL/TTL devices and the like, the Military wanted to define those better for themselves as well.  Thus in 1969 MIL-M-38510 was released.  38510, often called JAN38510 (Joint Army Navy Standard Naming which was used through Rev J in 1991) was a General Specification for Microcircuits.  It provided fit, form and function standards for various devices.  They could be made by anyone, anyway they liked, but to be marked/used as a JAN38510 device they had to meet what it defined that device to do.  This was all

Zilog JAN MIL-M-38510 52002BQA Z8002 CPU – 1987

based on existing devices, it simply took a commercial device, such as a 74181 ALU, and gave it a 38510 description and part number.  This ensured that no matter where the Military got that 38510 standard 74181 ALU it would behave the exact same.  The 38510 standard refer’d back to the MIL-STD-883 testing procedures, it in itself did not define any testing.

As things progressed, MIL-STD-883 with the how, and MIL-M-38510 with the what, NASA decided they should have their own standard (American government agencies like to compete).  Based on the 38510 standard,and the 883 testing standards NASA created MIL-STD-975 in 1976.  This was essentially a list of products that met NASA’s standards for all electronic devices.  Everything from capacitors, diodes, cables, oscillators and even some processors. Ultimately this was a great idea at the time.  It provided designers with a list of parts they could use that NASA had already certified as acceptable, rather then having to test/certify every single piece.  The cost and time saving were immense once the initial certification was done.  The list of certified devices was updated every few years through 1994 when the standard was canceled, likely because there was just too much new devices becoming available to keep up with.  Three levels of quality are used in this standard. Grade 1 parts arc very low risk, higher quality and

Illustration of the Ørsted spacecraft in orbit (image credit: DRSI)

reliability parts intended for critical applications (such as man rated space applications). Grade 2 parts are low risk, high quality and reliability parts for usc in applications not requiring Grade 1 parts. Grade 3 parts are higher risk, good quality and reliability parts but are not recommended for applications requiring high product assurance levels.

These particular SQ80C186s are made by Intel and listed as Grade 3 devices.  This is mainly because Intel decided not to take part in the NASA certification process, so their grading is based on their MIL-STD-883 QML (Qualified Manufacturer List) testing.  These parts were used on many satellite designs (such as PoSAT-1, Portugal’s first satellite in 1993 and the 1999-2014 Danish Ørsted Geomagnetic Mission)  as well as the International Space Station.  Its possible on the ISS they were used in a non-mission critical area where Grade 3 is acceptable.   Even as a Grade 3 device the replacement cost (in 2003) was $2,266.  Today they are a mere collectors item, as parts like these need to have a certified traceability with them, knowing where they have been and how/where they were stored is important to them being certified for use. These particular chips were made in 1993, a lot can happen in 27 years of storage and transport around the world.

Read More »

F-15 with P4 Instrumentation Pod – Looks like a missile under the wing, with blue and red stripe.

Quite the combination I know, but of course all related.  Last week I got some boards in that were quite interesting.  They were all fairly early serial numbered, from the 1980s and military in design.  Now one thing about anything military is identifying it is pretty hard to do, especially when it hails from an era before the Internet.  Many records from the 1980s have made it online, but OCR and transcription errors abound, a single wrong digit can turn an item made for a A-4 Skyhawk into a new blade from a lawnmower or a shiny new Navy mess tray.

Thankfully these boards all had a CAGE code which the US uses to identify each and every supplier.  In this case that code was 94987 which is Cubic Defense.  Cubic didn’t make lawnmower blades or mess trays but they did make a lot of instrumentation systems for aircraft (and they continue to do so).

F-16 with blue training pod under its left wing)

It turns out that training fighter pilots is best done without having to use live weapons, for obvious reasons, but in all other aspects should remain as true to lifer as possible, and then be able to be analyzed after that fact in order to learn from mistakes, and see who gets bragging rights for pulling the most G’s.  This means that the aircraft has to send and receive data as it would in combat, threat warnings have to go off when targeted, missiles have to be ‘launched (while being captive) at the appropriate times, and every aspect of the flight must be recorded, speed, roll rates, altitude, etc.

Cubic made pods, that attached to one of a fighters weapon hardpoints (typically the outermost) that did exactly that.  These pods interface with the aircraft’s flight systems (using the standard 1553 bus) as well as with ground based systems on the training range, forming a complete picture of what is going on between all the aircraft taking part.  These particular boards are from Cubic’s second generation digital pods, the P4 series (the first gen was, the P3). Specifically the P4A series.  Each pod contained a vast amount of sensors, antennas and instrumentation to monitor and record what was happening, as well determine if a missile as ‘launched’ to or from the fighter.

Cubic 185200-1 with Harris ID80C86 – The brains of the AN/ASQ-T25 P4AM Training Pod

At their heart was a Harris or Intel 80C86 processor, (Harris actually did the CMOS conversion on the 8086).  This is one of the earliest applications of the CMOS 8086.  In this case the 80C86 is running off of the normal 8284A clock generator and a 13.5MHz crystal. This results in a processor frequency of 4.5MHz, a bit under its 5MHz rating.  This is pretty typical of military applications, it generates less heat, draws less power, and gives more margins.  This particular board has a industrial spec CPU, later production versions had a full military qualified part (this board was a prototype).

Read More »

Socket 8 processors have something magical and I really enjoy working with them. Earlier I wrote about them more than once and it would seem that everything has already been said, but in this article you will find out which PC configuration is truly the fastest on Socket 8, although it never existed in reality. I just gave this platform what it never had, it’s like giving the first representatives of the Skylake processor architecture, which was released back in 2015, DDR5 and PCI-Express 4.0 today.

Before starting another fascinating story about Socket 8 and the processors that were installed there, I will give links to my previous experiments:

Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997
and what got us started…
Part 1: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997

As you can see, my close acquaintance with this socket has existed for a long time and over the past few years we have clearly managed to make friends. It would seem that all Socket 8 processors have been studied and tested in various configurations, including an insane configuration of six processors in such a monster as the ALR Revolution 6×6. But quite recently I got my hands on a motherboard made by ASUS, which gave me the opportunity to take a fresh look at the use of processors and the performance they are able to give in a newer platform.

What is this board and what chipset is it based on? To name the heroine of today’s article, I will first dwell on the main chipsets for Socket 8 processors. The first chipsets for Intel Pentium Pro processors appeared in November of 1995, 25 years ago. Already at that time, they understood that the future was behind the parallel execution of various tasks. The Intel 450KX chipset, codenamed “Mars”, was introduced for workstations, and the Intel 450GX “Orion” for servers. Mars allowed for dual-processor configurations, and the Orion officially supported up to four physical processors. Although on the example of the super-server ALR Revolution 6×6, which is based on Intel 450GX, the number of processors could have been much larger and could easily double the official figure.

Nowadays the term chipset is often associated with a single chip located on the motherboard, but when applied to the first chipsets for Intel Pentium Pro processors, we are dealing with the physical seven chips that made up the “number of special chips” or “chipset.” These chipsets supported slow FPM DRAM standard RAM, the server GX chipset could operate with 4 GB of such memory, while the KX “was content” with 1 GB support (Intel figuring a workstations needed less RAM then a server). By the standards of the second half of the 90s, these were immense volumes of RAM

In May 1996, a more progressive chipset appeared – Intel 440FX “Natoma”, which quickly began to replace older system logic sets. Intel 440FX itself already consisted of a pair of microcircuits, support for SMP, faster EDO / BEDO DRAM memory types along with the outdated FPM DRAM (though limited to 1GB max of RAM), a new version (2.1) of the PCI bus standard, as well as support for Intel Pentium-II processors were announced.

Most motherboards based on the Intel 440FX “Natoma” chipset have a physical design in the form of a Socket, where the processor was installed, but there were exceptions with a few using the new Slot 1 slot, where the first Pentium-II and Pentium Pro were installed through special slot adapters. A good example is the ASUS KN97-X motherboard with the included Socket 8->Slot 1 adapter called the ASUS C-P6S1.

ASUS KN97-X motherboard with ASUS C-P6S1 slocket adapter

Each manufacturer of such slot motherboards produced their own slot adapters, but due to their small circulation, finding them is now problematic. Socket 8 processors feel good in such adapters and the presence of a more modern infrastructure of such motherboards obviously contributes to an increase in performance. But Intel, having released the Intel 440FX chipset, decided to stop further support for its Socket 8 processors, although it could really have extended their life cycle.  Why just sell people a new motherboard chipset, when you cold ALSO force them to buy a new CPU to go in it?

Read More »

Since we have a complete, and very early mask set of the HP NanoProcessor (donated by Mr Bower, thank you) it seemed fitting to scan them in (tricky at 600 dpi and 6 scans each (they are around 40x60cm) then I sent them over (500MB) my friend Antoine Bercovici in France to stitch and clean, as well as remove the background.  THat allowed this cool animation of the mask being built.
These are made from a set of 100X Mylar masks

Here you can see how the 6 different mask layers are built up.  The last mask layer (black) is the bonding pads
Each individual layer is also shown, some are very simple, while others contain a lot more.

In the lower left corner of the masks you can see their layer number 1B 2A 3A…etc

You can see the original HP part number on the mask 9-4332A as well as ‘GLB’  GLB is a composition of the initials of the two designers of the chip: George Latham and Larry Bower.

Here is a larger version as well: HP NanoProcessor Mask Set

Original Nanoprocessor prototypes from 1974-75. Note hand written wafer number, open die cover and early part number (94332)

Back in the 1970’s the Loveland Instrument Division (LID) of HP in Colorado, USA was the forefront of much of HP’s computing innovation.  HP was a leader, and often THE leader in computerized instrumentation in the early 1970’s.  From things like calculators, to O-scopes to desktop computers like the 9825 and 9845 series.  HP made their own processors for most all of these products.  The early computers were based on the 16-bit Hybrid processor we talked about before.  At around the same time, in 1974, the HP LID realized they needed another processor, a control oriented processor that was programmable, and could be used to control the various hardware systems they were building.  This didn’t need to be a beast like the 16-bit Hybrids, but something simpler, inexpensive, and very fast, it would interface and control things like HPIB cards, printers, and the like.  The task of designing such a processor fell to Larry Bower.

The result was a Control Oriented Processor called the HP nanoprocessor.  Internally it was given the identifier 94332 (or 9-4332), not the most elegant name, but its what was on the original prototypes and die.   The goal was to use HP’s original 7-micron NMOS process (rather then the new 5-micron NMOS-II process) to help save costs and get it into production quickly.

Nanoprocessor Features – Note the speed has been ‘adjusted’

The original design goal was a 5MHz clock rate and instructions that would execute in 2 cycles (400ns).  The early datasheets have this crossed out and replaced with 4MHz and 500ns, yields at 5MHz must not have been high enough, and 4MHz was plenty.

Handwritten Block diagram

The Nanoprocessor is interesting as it is specifically NOT an arithmetic oriented processor, in fact, it doesn’t even support arithmetic.  It has 42 8-bit instructions, centered around control logic.  These are supported by 16 8-bit registers, an 8-bit Accumulator and an 11-bit Program Counter.  Interface to the external world is via an 11-bit address bus, 8-bit Data bus and a 7-bit ‘Direct Control’ bus which functions as an I/O bus.  The nanoprocessor supports both external vectored interrupts and subroutines.  The instructions support the ability to test, set and clear each bit in the accumulator, as well as comparisons, increments/decrements (both binary and BCD), and complements.

Here is one mask (Mask 5 of 6) for the prototype Nanoprocessor. You can see its simplicity.  On the bottom of the mask you can see the 11-bit address buffers and Program Counter

2.66MHz 1820-1691 – note the -5V Bias Voltage marked on it

The Nanoprocessor required a simple TTL clock, and 3 power supplies, a +12 and +5VDC for the logic and a -2VDC to -5VDC back gate bias voltage.  This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC).  Each chip was tested the and voltage was hand written on the chip.  The voltage was then set by a single resistor on the PCB.  Swapping out a Nanoprocessor meant you needed to make sure this bias voltage was set correctly.

If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL).  Even with an external ALU the Nanoprocessor was very fast.   The projected cost of a Nanoprocessor in 1974 was $15 (or $22 with an ALU),  In late 1975 this was $18 for the 4MHz version  (1820-1692) and $13 for the slower 2.66MHz version (1820-1691).

At the time of its development in 1974-1975 the Motorola 6800 had just been announced. The 6800 was an 8-bit processor as well, made on a NMOS process, and had a maximum clock rate of 1MHz.  The initial cost of the 6800 was $360, dropping to $175, then $69 with the release of the 6502 from MOS.  By 1976 the 6800 was only $36, but this is still double what a Nanoprocessor cost

An early ‘slide deck’ (the paper version equivalent) from December 1974 sets out the What Why and How of the Nanoprocessor.  The total cost of its development was projected to be only $250,000 (around $1 million in 2020 USD).  The paper compares the performance of the Nanoprocessor to that of the 6800.  The comparisons are pretty amazing.

Interrupted Count Benchmark

For control processing interrupt response time is very important, the Nanoprocessor can handle interrupts in a max of 715ns, compare that to 12usec for the 6800.   The clock rate of the Nanoprocessor is 4 times faster but the efficiency of its interrupts and instructions are what really provides the difference here.

The clock rate difference (1MHz vs 4) really shows here, but the Nanoprocessor is also executed 3 times the instructions to do the same task, and still is faster.

Even using an external ALU compared to the Motorola’s internal ALU, the nanoprocessor is better then twice as fast (thanks here to its much higher clock frequency)

Full Handshake Data Transfer. Interfacing to the outside world was the main driver of the Nanoprocessor. Here we see that it can ‘talk’ to other devices much faster then the 6800

All instructions on the Nanoprocessor take 500ns to execute compared to the 1-10u for the 6800.

Today we do benchmarks based on framerates in games, or render times, but you can see that benchmarks were even important back then.  How fast a processor could handle things determined how fast the printer could be, or how fast it could handle external data coming in.  It’s no wonder that the Nanoprocessor continued to be made into the late 1980’s and many of them are still in use today running various HP equipment.

Nanoprocessor User Manual – October 1974

A big thank you to Larry Bower, the project lead and designer of the Nanoprocessor, who donated several prototypes, a complete mask set, and very early documentation on the Nanoprocessor (amongst some other goodies)

Documentation so ealy it has many hand written parts, and some corrections.  This had to be a very annoying oops if it wasn’t caught early on.  Even Engineers get their left and right mixed up on occasion

It took way longer then it should have but over the last 5 weeks CPUShack.com was transitioned to a new server.  We were hosted on a Media Temple GRID server, which got less and less suited for WordPress over the years so ended up with hundred of dollars in overages everytime i posted an article.  CPU Shack is now on a virtual dedicated server which should be faster and more flexible.  Next step will be to add SSL support, to keep up with current web guidelines.

If you notice anything not working, be sure to let me know.

AMD AM29C327 Engineering Sample -1990

Recently I came across one of the more unusual members of the AMD Am29300 series.  These were a set of processor elements (multipliers, FPUs, ALUS, registers) AMD designed to support AM29000 CPUs as well as for the bases for custom CPU designs.  Some. like the AM29C323 multiplier found common use in video game and other applications.  Others like the AM29C325 32-bit FPU were used in educational experiments and research.  The 29300 (Bipolar) and 29C300 (CMOS) series are not particularly well known due to their obscure and often deeply specialized used.  At the top of the series lies the AMD AM29C327 Double precision (64-bit) FPU.  This FPU has a few tricks up its sleeves and is about as obscure in use as it gets….

The Am29C327 was on of the first chips made on AMDs CS-11A 1.2u processor (an enhancement of the 1.6u CS-11) .  It was first announced in 1987 with sampling to begin in late 1988.  The ‘327 contained over 250,000 transistors and was packed in a 169PGA package.  It is a IEEE754 compliant double precision FPU but also supports IBM and DEC formats.  It has 3 32-bit buses (2 for input and one for output) that, when multiplexed, allow for 64-bit maths.  Its little brother, the ‘325, only supports 32-bit math, and comes in a 145PGA package with around 30,000 transistors (11,000 gates).  So why does going to double precision involve nearly 10 times the transistor count?  It turns out that the ‘327 is more closely related to an actual CPU then a normal FPU.  The ‘325 has all of 8 instructions (add/sub, mult const subtraction and some conversions), while the ‘327 supports 58 instructions.  Of those 58 instructions 35 are Floating point, 1 is system management, and the other 22? Those are a full set of integer instructions.  The ‘327 actually supports more then just floating point.  Its internal ALU is a 64-bit 3 input design, allowing inputs from either the 2 external inputs, the output, a set of 8 64-bit registers, or a set of 6 constants.  Its instructions are 14 bits and it supports pipelining for even faster calculations.  Interestingly, pipelining can be disabled and the FPU will work in straight flow through mode.  So where is such a complicated chip used? Doing complicated math of course.

Read More »