Zycad IU – Interface Control Processor for the XP series of Emulators. Fab’d by LSI in 1990

Zycad was founded in 1981 to develop and market simulation acceleration technology.  This was to allow new chip designs to be tested/simulated before being laid out in silicon, providing the possibility to catch faults earlier in the design process.  The earlier faults can be caught, the easier, and less expensive they are to fix.

By the late 1980’s Zycad a leader in simulation tech and set the standard for simulation systems.  They provided the simulation software environment, a simulation/hardware descriptive language (Zycad Intermediate Format), as well as custom hardware accelerators for the logic/fault simulation.

In 1987 Zycad shipped a customized system to LSI, which LSI was then able to use, and market for all their customer designs, notable the LSI version of the SPARC processor.  This close relationship with LSI also benefited Zycad, as it was LSI who fab’d Zycad’s custom silicon, the heart of their emulation system. In the late 80’s and early 90’s the main Zycad emulation system was the XP series.  The XP series (consisting of the 100, 140 and 200) was based on 2 main IC’s.  The Interface Control Processor (IU) was the interface between the host processor (either a SPARC system, or a VAX type workstation) and the Logic/Fault Emulation Processors (PU’s).  One IU could control multiple PU’s and a typical system (such as the XP-140) had 1 IU and 5 PU’s.  These systems could emulate from 256,000 (XP-100) to 4 million (XP-200) gates at speeds from 2.5 millions events/sec to 40 million events/sec.

Zycad XP-140 system board with 1x IU and 5x PU Emulation processors

In 1996 Zycad announced the Lightspeed simulation server, massively parallel simulation server running on from 64-4096 processors, each with their own on chip memory.  These were implemented on 0.5u ASICs from LSI.  This technology was sold later that year to one of Zycad’s competitors, IKOS, leaving Zycad to enter the field of FPGAs as Gatefield, which later would be bought out by Actel.  IKOS was later acquired by Mentor Graphics, a company that worked extensively with Zycad and their emulators in the 1980’s and 1990’s.  The customer, had now become the owner.

What Zycad began in the 1980’s continues today on a massive scale.  The XP series and the later Lightspeed simulation server are in many ways similar to the Palladium and Palladium II processors by Quickturn/Cadence that we discussed lat year.

Hardware simulation is a field that continues to grow in scale and complexity.  As systems become more and more complex, transistors counts continue to rise, and the need to make sure it works, before putting it in silicon remains.

Cadence Palladium II Processor MCM 1536 cores – 128MB GDDR – Manufactured by IBM

Several years ago we posted an unusual MCM that’s purpose was a mystery.  It was clearly made by IBM and clearly high end.  While researching another mystery IBM MCM both of their identities came to light.  The original MCM is an emulation processor from a Cadence Palladium Emulator/Accelerator system.

In the 1990’s IBM had been working on technology to make emulating hardware/software designs more efficient as such designs got more complicated.  At the time it was most common to emulate a system in an FPGA for testing, but as designs grew more complex this became a slower and slower process.  IBM developed the idea of an emulation processor.  This was to be known as CoBALT (Concurrent Broadcast Array Logic Technology).  It was licensed to a company called QuickTurn in 1996.  At its heart the QuickTurn CoBALT was a massively parallel array of boolean logic processors.  Boolean processors are similar to a normal processor

Here is a flipped (and very rough) die from a Palladium II. You can make out the very repeating design of the 768 boolean processors.

but only handle boolean data, logic functions such as AND, OR, XOR, etc.  Perhaps the most well known, is the boolean sub-processor that Intel built into the 8051, it excelled at bit manipulation.  The same applies for the emulation processors in CoBALT.  Each boolean processor has at its heart a LUT (Look Up Table), with 8-bits to encode the logic function (resulting in 256 possible logic function outputs) and the 3 gate inputs serving as an index into the LUT, as well as the associated control logic, networking logic, etc.

A target design is compiled and emulated by the CoBALT system.  The compiling is the tricky part, the entire design is broken down into 3-input logic gates, allowing the emulator to emulate any design.  Each processor element can handle one logic function, or act as a memory cell (as many designs obviously include memory).  The CoBALT had 65 processors per chip, and 65 chips per board, with a system supporting up to 8 boards.  This 33,280 processor system could compile 2 Million gates/Hour.  The CoBALT plus sped this up a bit and supported 16 boards, doubling capacity and added on board memory.

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