Cypress CY7C601-25GC – First package with heatspreader – Omitted on later versions

In Mid-1987 Sun Microsystems (now owned by Oracle) released the SPARC (Scalable Processor ARChitecture)  processor architecture to be used in their computers (replacing the 68k based systems they had previously used).  The SPARC was designed from the outset to be an open architecture, allowing manufactures to license and built processors that implemented it using whatever technology they wished.  The goal of this was to 1) build a large SPARC ecosystem and 2) keep prices in check by fostering competition among manufacturers.  The SPARC is still used today by Oracle, Fujitsu, the European Space Agency and others, owing largely to its design as an open architecture from the very beginning.

The first version was made by Fujitsu on a 20,000 gate array at 1.2 micron and ran at 16.6MHz.  In July 1988 Cypress  (later to be spun off as Ross and make the famous HyperSPARC line) announced the CY7C601.  This was the fastest implementation of the SPARC at the time.  It was made on 0.8u CMOS process and contained 165,000 transistors, dissipating around 3.3Watts.  As was typical of many processor designs of the time, it was an integer only processor, requiring a separate chip (the CY7C602) for floating point work.  In September of 1988, Cypress cross licensed the ‘601 to Texas Intruments in exchange for rights to the 8847 floating point processor.  This was mainly to appease one of Cypress main customers who demanded that a second source for the ‘601 chips be available, a demand more common in the 1970s then in 1988 but Cypress obliged.  Cyrpress also gained the rights to make the next generation SPARC processor that TI was developing.  TI would go on to make many SPARC processors, and continued to be the primary fab for Sun up through the SPARC T2 Plus in 2008.  Oracle now used TSMC to fab the T3 and T4 SPARC processors.

Fairchild developed the Clipper architecture in 1986, and sold it to Intergraph in 1987.  The design never enjoyed wide success and was only used in systems made by Integraph, as well as some by ‘High Level Hardware.’  The deign itself was RISC like and competed mainly with the Sun SPARC processors.

The final version was the C400 which was released in 1993 (preceded by the C100 and C300). Presumably there was a C200 but I have not seen any documentation on it.  The C400 ran at 50MHz (like the C300) and actually consisted of 3 separate chips. The CPU, the FPU and the CAMMU (Cache/Memory Management Unit).  Intergraph developed their own version of UNIX called CLIX to run on the clipper, and demonstrated a version of Windows NT that ran on the C400 as well. Ultimately the lack of software support, and the slow adoption killed the Clipper.  While Intergraph was designing the C5, Intel assured them a good supply of processors, and this convinced Intergraph to cancel the C5.

Intergraph C4 MCM

It was also available as a MCM (multi-chip-module) incorporating all three dies in a single ceramic package.  This is one of the nicest looking MCMs I have seen, unfortunately the bottom plate was missing when I got it, but the dies are at least visible.  I unfortunately am not sure which die is which so if you know, let me know.

So I bought some chips on eBay, they arrived, and are New Old Stock, made in 2004, really fairly recent.  I have a datasheet for them that is marked Winbond which I found rather strange, since the chips, as you can see are marked National. This in itself isn’t super unusual. Occasionally a smaller company will use a larger companies markings to get design wins. The larger company acts in essance like a co-signer, validating and approving of the design.

National PC97551

Winbond isn’t small though, and the datasheet was marked 2006.  A quick look on Winbond’s site shows no info on this chip. Turns out Winbond spun off their controller business to a company called Nuvoton. And  how did Winbond get the desgin? Yup, National sold off their Super I/O and embedded controller division to Winbond in 2005.

And it is of course a processor, in this case a 16bit RISC processor running at 20MHz based on the (formerly) National CompactRISC architecture.

When designing a system, the best performance is often reached by using an ASIC, you can customize it to your design and tweak it for maximum performance.  This, however, adds costly development time, and little flexiblility.  You could use a general purpose processor; this saves dev time, and cost, but at the expense of performance.  What if you could have both? Off the shelf processor technology, AND customizable speed.

You can. This is what Software Configurable Processors are designed for. In simple terms they are a standard CPU core, wrapped in a FPGA.  This way istructions for the processort can be configured for maximun speed.  If you have a function in your code that is repetitive, it can be reduced to a single instruction for the processor.

One of the leaders in Software Configurable Processors is called Stretch. Their S6000 line of processors use a Tensilica Xtensa core (a VLIW RISC design), wrapped in a custom FPGA. In this way the RISC core can be programmaed on the fly, providing much faster performance then a normal processor, or DSP.

Automotive computing in manyways is similar to your personal computer, and the same inherent problems.  On your PC it is good to have the OS  isolated from the normal applications (especially the internet browser). Same thing in your car, you do not want the navigation and media player functions to be able to interfere or crash the control computer.  This is why most cars have DOZENS of computers.  Renesas has just announced the SH7776, a dual SH-4A cored CPU. One core for the information systems, and one for the control systems.  They share a common memory set, but it is segmented to prevent any problems.  Each core runs at a whopping 533MHz and can output almost 2000 MIPS.

Clearly thats not enough for Renesas, they through in a graphics core too, a PowerVR core with 3D Rendering.

Source: EEProduct Center