ST STi5500 – The Original 50MHz Transputer based Omega

In January ST announced that they would be exiting the Digital Set Top Box (STB) market.  This is a market that they arguably led for the last 20 years, and one that really began with their Omega processor in 1997. The ST Omega processor line, beginning with the STi5500 powered set top boxes, for cable companies, satellite companies, and DVR’s as well as other TV connected devices.  Open up a satellite TV receiver from the last 20 years and you are very likely to find a STi Omega chipset.

The STi5500 was the beginning, and interestingly at its core was a ST20 processor, based on the Inmos Transputer (which ST now owned) from the late 1980’s.  The Transputer was meant to revolutionize computing, making processors so cheap, that they could be embedded into pretty much any other logic device, what today we call an SoC, but in 1985, was a novel idea.  At the time it didn’t really succeed, but ended up seeing its intended use 10+ years later in the Omega.  In the 1980s the Transputer saw speeds of up to 30MHz, int he STi5500 it ran at 50MHz with 2K of I-cache + 2K of Data Cache as well as 2K of SRAM that could be used as data cache.

ST STi5514 – Enhanced 180MHz Omega

In the early 2000s the Omega was upgraded to a faster ST20 core, eventually hitting 243MHz in the STi5100, now with the caches increased to 8K each, as well as 8K of SRAM.  This was getting to be the limit of the ST20 Transputer core.  ST needed a core that could support higher speeds running such things as Java and Windows CE amongst other things, as well as support the higher resolutions and audio quality requirements.

ST handled this is in two entirely different ways.  First they licensed the SH-4 32-bit RISC core from Hitachi, a rather surprising move but STBs was not a market Hitachi was in, so it was in both companies best interest.  ST also was working on their own new core to replace the ST20, and they had help, from a very surprising partner.

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TiMedia TM-1300 – Marketing Sample

The roots of TriMedia start in 1987 at Philips with Gerrit Slavenburg (who wrote actual forwards for most of the Datasheets) and Junien Labrousse as the LIFE-1 processor.  At its heart it was a 32-bit VLIW (Very Long Instruction Word) processor. VLIW was a rather new concept in the 1980’s, and really didn’t catch on until the late 90’s.  Intel’s i860 could run in superscalar, or VLIW mode in 1989 but ended up a bit of a flop.  TI made the C6000 lince of the TMS320 DSP which was VLIW based.  By far thos most famous, or perhaps infamous, VLIW implementation were the Transmeta, and the Itanium, both of which proved to be less then successful in the long run (though both ended up finding niche markets).

TriMedia, released their first commercial VLIW product in 1997, the TM1000.  As the name suggests, TriMedia Processors are media focused.  They are based around a general purpose VLIW CPU core, but add audio, video and graphics processing.  THe core is decidedly not designed as a standalone processor.  It implements most CPU functions but not all, for example, it supports only 32-bit floating point math (rather than full 64 or 80 bit).

The TM-1300 was released in 1999 and featured a clock speed of 166MHz @ 2.0V on a 0.25u process.  At 166MHz the TM-1300 consumed about 3.5W, which at the time was relatively low.  It had 32K of Instruction Cache and 16K of Data Cache. As is typical of RISC processors the 1300 had 128 general purpose 32-bit registers. The VLIW instruction length allows five simultaneous operations to be issued every clock cycle. These operations can target any five of the 27 functional units in the processor, including integer and floating-point arithmetic units and SIMD units.

The above picture TM-1300 was a marketing sample handed out to the media during the Consumer Electronics Show for the processors release in 1999.  It is marked with the base specs of the chip as well as CES SAMPLE.  Likely these were pre-production units that didn’t meet spec or failed inspection, remarked for media give-aways.

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Last week we talked about Software Configurable Processors, and how they bridge the gap between general purpose CPU’s and FPGA’s. Yesterday a pair of them came in the mail.

Stretch S6000 & S6106

The S6100 is Stretch’s flagship product at this point (4 data ports full AIM interface and PCIe running at 345MHz).  The S6106 is the low power device (2 data ports no AIM and no PCIe, clocked at 167MHz).  This particular S6106 is an Engineering Sample.  They are both based on the Xtensa VLIW core. (pic after the break)

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When designing a system, the best performance is often reached by using an ASIC, you can customize it to your design and tweak it for maximum performance.  This, however, adds costly development time, and little flexiblility.  You could use a general purpose processor; this saves dev time, and cost, but at the expense of performance.  What if you could have both? Off the shelf processor technology, AND customizable speed.

You can. This is what Software Configurable Processors are designed for. In simple terms they are a standard CPU core, wrapped in a FPGA.  This way istructions for the processort can be configured for maximun speed.  If you have a function in your code that is repetitive, it can be reduced to a single instruction for the processor.

One of the leaders in Software Configurable Processors is called Stretch. Their S6000 line of processors use a Tensilica Xtensa core (a VLIW RISC design), wrapped in a custom FPGA. In this way the RISC core can be programmaed on the fly, providing much faster performance then a normal processor, or DSP.