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Open RISC MIPS. R10000 Processor Debuts MIPS ANDES Architecture and MIPS Avalanche Bus for Breakthrough Speed

MOUNTAIN VIEW, Calif. (October 17, 1994) -MIPS Technologies, Inc. and two semiconductor partners, NEC Electronics Inc. and Toshiba America Electronic Components, Inc., today announced the company's next-generation MIPS RISC microprocessor design, the MIPS R10000, formerly code-named T5. The single-chip superscalar 64-bit microprocessor features numerous innovations including the new MIPS ANDES architecture (Architecture with Non-Sequential Dynamic Execution Scheduling) and MIPS Avalanche bus to optimize the R10000 microprocessor's performance on real applications. On initial simulated benchmarks, the R10000 processor boasts estimated SPECint92 performance of over 300 and SPECfp92 of more than 600. The R10000 microprocessor runs both Windows NT and UNIX operating systems and runs all existing software applications developed for the R4000 family of processors without modification.

"MIPS reinvents the microprocessor with the R10000," said Tom Whiteside, president of MIPS Technologies, Inc. "The R10000 processor and its ANDES architecture break the chief bottleneck in microprocessor performance, which is not sheer speed, but feeding data and instructions. The result is profound, and it will be reflected in the way MIPS accelerates real applications rather than something that will show up in an artificial measure like SPECmarks. When you look at the way real applications run, the R10000 processor outdistances everything."

The R10000 microprocessor is designed for a broad spectrum of computing needs, spanning from PCs and workstations to servers and supercomputers. It is especially optimized for database and visualization performance. For the first time ever, many of the bottlenecks common to database performance have been specifically addressed at the microprocessor level with the R10000 microprocessor. While the R10000 processor is a powerful engine for technical computing, it will also enable new commercial applications such as client/server computing, and large database and digital media applications.

Like the MIPS R4000 family, the R10000 microprocessor is inherently designed forsymmetric multiprocessing, so up to several hundred chips can be closelycoupled in a computer to offer superior performance on applications traditionally solved by large, expensive mainframe and supercomputers. The R10000 processor also features a direct connection multiprocessing feature to enable development of cost-effective multiprocessing computers with up to four R10000 processors directly tied together on a single cluster bus. This direct connect feature could give rise to a new breed of powerful, affordable desktop or deskside systems for the Windows NT or UNIX operating systems.

By combining dynamic scheduling with non-blocking caches, the R10000 microprocessor gains much of its performance. With dynamic scheduling, the processor can operate at its highest efficiency by reordering instructions to suit the available execution unit resources. The instructions can then be executed and completed out of order and then reordered or "graduated" back in their original order. This dynamic scheduling makes the fullest use of the microprocessor's extensive execution units and keeps them from going idle. Non-blocking caches keep the processor active while waiting for data it may need for a later operation.

The four-way superscalar R10000 microprocessor can fetch four instructions and issue up to five instructions per cycle. Furthering its performance, the R10000 processor has five independent fully pipelined, low-latency execution units. To speed data flow the processor supports large register files and features a large on-chip primary cache with 32 kilobytes for instructions and 32 kilobytes for data. The R10000 microprocessor also features an on-chip secondary cache controller for supporting 512 kilobytes to 16 megabytes of synchronous secondary cache. Both the primary and secondary caches are two-way set associative. The innovative MIPS Avalanche bus enables split transactions, the ability for two or more operations to overlap their execution at the same time. The Avalanche bus allows holding up to eight outstanding transactions at one time prior to execution.

The R10000 microprocessor is another result of MIPS' unique Open RISC business model. Leading computer systems manufacturers including NEC Technologies, Tandem Computers, Pyramid Technology, Siemens Nixdorf AG and Silicon Graphics have been involved in the design of the R10000 processor since its beginning. These systems companies all have equal, early access to the next generation MIPS processor. They are already designing systems based on the R10000 microprocessor. Two of the world's leading semiconductor companies, NEC Electronics and Toshiba America Electronic Components, Inc., have also been directly involved in the R10000 design.

The R10000 processor has a die size of 297.6 square millimeters and approximately 6 million transistors. It is designed for implementation in 0.5 micron CMOS. The initial partners for the MIPS R10000 microprocessor are NEC Corporation and Toshiba Corporation. Samples are targeted to become available in the first half of 1995.

Insight From MIPS Partners

"By leveraging the processing power of T5 and next-generation operating systems such as Windows NT, NEC can respond to the performance demands of high-end systems designers," said Ichiro Fujitaka, vice president of NEC Electronics Inc. "In addition, NEC's advanced process technology and volume manufacturing capacity will enable customers to deliver cost-effective solutions for high-performance computing."

NEC Electronics Inc., headquartered in Mountain View, Calif., manufactures and markets an extensive line of electronic products including ASICs, microprocessors and microcontrollers, digital signal processors (DSPs), memories and components. The company operates a 676,000 square-foot manufacturing facility in Roseville, Calif. NEC Electronics Inc. is an affiliate of NEC Corporation (NIPNY), a $31 billion international manufacturer of computer, communications and semiconductor products.

"We are pleased to be a technology partner for this latest RISC development with MIPS Technologies," stated Bob Brown, executive vice president, group executive for Toshiba America Electronic Components, Inc. "The R10000 design, combined with the ANDES architecture, promises to leapfrog other microprocessors on both performance and low cost factors. This will provide our customers with a viable alternative to traditional microprocessor offerings."

Toshiba America Electronic Components, Inc. (TAEC) is the American manufacturing, sales and marketing arm of one of the world's largest suppliers of semiconductors, integrated circuits and electronic components for industrial and consumer applications. The company is the recognized leader in CMOS technology and has one of the broadest IC product lines in the industry. In addition, Toshiba is a leading manufacturer of technologically advanced electron tubes and solid state devices, including color picture tubes, liquid crystal displays, medical tubes, lithium ion batteries, microwave components, laser diodes and optical transmission devices. The company is located at 9775 Toledo Way, Irvine, Calif.

MIPS Technologies, Inc. designs and supplies the world's most advanced RISC microprocessor technology. The company tests, certifies and licenses its processor technology to its semiconductor partners which provide processors for the computer system and embedded control markets. MIPS microprocessors power systems from a number of computer industry leaders, including Acer Technologies, Deskstation Technology, Pyramid Technology, Siemens Nixdorf AG, Silicon Graphics, Inc., Sony Corporation, Tandem Computers Incorporated, NEC Technologies, Inc., NeTpower Inc. and Tektronix, Inc. MIPS RISC architecture components are available from world-class semiconductor companies. MIPS Technologies, Inc. is a wholly owned subsidiary of Silicon Graphics, Inc. and is headquartered in Mountain View, Calif.


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