Today at the Microprocessor Forum, IBM disclosed the first details of a new family of powerful 64-bit microprocessors that will provide new levels of performance for the hardest working, number-crunching workstations, servers and super computers. Called POWER3, the family is the latest in a line of high-performance RISC (Reduced Instruction-Set Computing) microprocessors developed for IBM's UNIX-based systems. It incorporates design features from IBM's POWER microprocessors -- such as a highly superscalar processing unit and the industry's most robust memory bandwidth -- with the scalability of the PowerPC architecture to provide unprecedented system throughput and performance for IBM's RS/6000 systems.

The initial POWER3 microprocessor has already sampled to the RS/6000 product group and will ship in systems in 1998. The POWER3 will be produced using IBM's advanced manufacturing process technologies -- including those with copper interconnection -- and achieve clock speeds of more than 500 MHz and performance exceeding 70 and 30, respectively, on the SPEC95 floating-point and integer benchmarks.

"The new POWER3 family will give RS/6000 customers the performance to run computer simulation programs that result in safer jets, more efficient cars and new disease-fighting drugs," said Tony Befi, vice president of development, IBM RS/6000 Division. "We're eager to help our customers put this technology to work to achieve their business goals."

New superscalar processor design has industry's leading memory bandwidth
The performance of the POWER3 family is made possible by a new highly superscalar processor design that can execute eight instructions per processor cycle and high memory bandwidth, or "pipelines," to continuously feed vast amounts of instructions and data to the processor core. The superscalar design and high bandwidth are key performance-determining factors on compute-intensive technical and commercial applications, such as computer-aided design, meteorological simulations, data mining and on-line transaction processing. The POWER3 processor, as with the POWER chips before it, will deliver the highest levels of performance to RS/6000 systems customers using these and other mission-critical applications. The processor core design has two independent, full floating-point units, three independent fixed-point units and two load/store units along with aggressive out-of-order and speculative execution and other sophisticated features.

Supplying the processor core are two high-bandwidth buses: a 16-byte PowerPC 6XX architecture bus to main memory and a dedicated 32-byte bus to the L2 cache that can run at the same speed as the processor. For example, at 200 MHz, the processor has throughput of 6.4 GB (gigabytes) per second from the L2 cache, which is more than double the bandwidth of any processor available today. POWER3 also has an advanced on-chip 64-KB data cache and a 32-KB instruction cache with numerous unique and advanced features to further enhance the flow of instructions and data to the processor core.

PowerPC architecture provides unprecedented scalability
The POWER3 design is based on the highly scalable PowerPC architecture, IBM's strategic architecture used in its designs for embedded controllers to desktop-class processors to high-end processors. The PowerPC architecture provides the ability for thousands of POWER3 microprocessors to be combined into a single, unified computing unit. The POWER3 processor will be at the heart of a 4096-processor RS/6000 SP (Scalable Parallel) super computer delivered to the U.S. Department of Energy at Lawrence Livermore Labs as part of the Accelerated Strategic Computing Initiative (ASCI). When the system is upgraded with POWER3 processors in 1998, the system will deliver a whopping 3.0 trillion floating-point calculations (teraFLOPS) per second, which IBM expects will make it the fastest computer in the world.

Design exploits IBM process technology
The POWER3 microprocessor family will use IBM's most advanced chip manufacturing technologies. The initial version of the POWER3 processor will be manufactured in IBM's .25-micron process technology, CMOS 6S2, and future versions -- that will be sampling in 1998 -- will be manufactured in IBM .20-micron CMOS 7S. CMOS 7S was recently announced as the first manufacturing technology to use copper interconnection technology instead of traditional aluminum wiring.