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May 12, 1997
MOUNTAIN VIEW, CA (May 12, 1997) -- Silicon Graphics, Inc., (NYSE: SGI) today
announced a MIPS® microprocessor roadmap, unveiling three successive 64-bit
family designs, the MIPS R12000TM processor
followed by the code-named H1 and H2 generations, that will bring new levels of
high performance computing to Silicon Graphics® and other computer systems.
The H1 and H2 designs are expected to achieve very high levels of computing
performance by maximizing memory bandwidth and eliminating processor-to-memory
bottlenecks. With their expanded bandwidth capacities, the new designs will
move and process tomorrow's larger and more complex types of data on and off
the processor as fast as possible.
"Silicon Graphics has always focused on providing the high bandwidth required to transfer graphics images and to build large scalable systems," said Edward R. McCracken, chairman and chief executive officer of Silicon Graphics. "We're going to extend this crucial advantage by building bandwidth right into the microprocessor itself. With our MIPS microprocessor and system design teams working together, we can build systems from the ground up to maximize performance on targeted applications."
Memory bandwidth and memory latency are the most critical problems for future microprocessor design, according to John Bourgoin, president of the MIPS Group of Silicon Graphics. "Without addressing these two issues, increasingly larger and more complex applications will choke the system due to contention for memory bandwidth and processor-to-memory latency," Bourgoin said.
Until now, increasing CPU core clock speeds alone allowed processors to boost application performance. However, because clock speeds have increased at a faster rate than memory interface speeds, this technique results in relatively higher memory latency and proportionally, slower overall application performance. In fact, processor-to-memory latency is today's most critical processor design challenge. The currently shipping MIPS R10000TM processor improves memory latency tolerance by combining out-of-order execution with a split-transaction bus, as will the future MIPS R12000 design. These features allow the processor to dynamically reorder and execute instructions, thereby reducing stalls and decreasing the effects of memory latency.
In the future, delivering the highest application performance will also depend on memory bandwidth capacity and how this maximizes data transfer efficiency on and off the processor. As CPU cores become faster and microarchitectures wider, CPU cores must be supplied with instructions and data at faster rates, intensifying the need for greater bandwidth. At the same time, the fact that CPU clock speeds continue to outstrip memory interface speeds increases the need for bandwidth to offset the effects of latency. The growing size and complexity of software application codes also present challenges. For example, object-oriented or multithreaded applications strain cache capacity, adding to the bandwidth and I/O burden. The problem of available memory bandwidth becomes especially acute when scaling to large multiprocessor systems, given the memory overhead associated with building large cache coherent systems.
MIPS R12000 - Higher Speeds and New Features
By scaling the R10000 design up in clock speed, with significant modifications to ensure a corresponding increase in application performance, Silicon Graphics is extending the R10000 family with the MIPS R12000 design. While maintaining instruction set and socket compatibility with the current processor, the R12000 design offers a CPU speed increase to 300 MHz. Other new optimizations include increasing the number of out-of-order instructions from 32 to 48, adding a 32-entry, two-way branch target cache and quadrupling in size the branch prediction table. Volume production of the R12000 is planned for the first half of calendar 1998.
World's Highest Memory Bandwidth
The next-generation processor family after the R10000 family (including the R12000), code-named H1, is expected to effectively eliminate bottlenecks between the CPU and memory by providing 5 gigabytes per second of memory bandwidth, a six to tenfold increase in memory throughput over current MIPS processors. H1 implements a new microarchitecture that fully exploits this dramatically increased memory bandwidth, making it especially suitable for powering large commercial and technical applications.
H1 will be the first implementation of the next-generation MIPS V instruction set, maintaining code and instruction set compatibility with the MIPS IV R10000 family. MIPS V is designed to offer superb performance for 3D geometry processing, oil and gas, and manufacturing applications. For optimizing digital media applications such as image processing, real-time video compression and decompression, and professional authoring and compositing, H1 will support MIPS Digital Media Extensions (MDMX), an application-specific extension. H1 is scheduled for volume production in the first half of calendar 1999. Multiple speed iterations of H1 will follow over two years.
Industry-leading Functional Integration
H2 is a new microprocessor family being designed for the world's most demanding technical and commercial computing applications which customers will be using into the next decade. Drawing upon Silicon Graphics' expertise in rapidly moving large data sets in and out of the CPU in single and multiple processor environments, the new family integrates an innovative memory interface that blurs the traditional boundary between processor and system design. While maintaining code and instruction set compatibility, H2 is expected to power large scalable server class machines to desktop systems.
MIPS microprocessors are manufactured and shipped by its world-class semiconductor partners: Integrated Device Technology, Inc.; LSI Logic Corporation; NEC Corporation; NKK Corporation; Philips Semiconductor; Quantum Effect Design (QED) and Toshiba Corporation. These partners offer state-of-the-art manufacturing process technology, and also provide custom integration, derivative design technologies and other value-added competencies that help make MIPS the world’s leading RISC architecture.