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EMBEDDED: NAT SEMI DEVELOPS RISC-CISC HYBRID (October 21st 1994) National Semiconductor took the plunge and introduced a whole new RISC instruction set this week, in an attempt to woo the embedded market. Project "Pirahna" looks conceptually similar to Motorola's ACE/ColdFire project (see story 1201) - an attempt to combine the best of RISC and CISC models to benefit the embedded market.
Piranha is described as a common RISC architecture that can scale from 8-bit to 32 bit implementations. Its brief - to avoid "RISC bloat" - the relatively high amounts of memory which RISC requires to store its programs. Whereas other manufacturers (IBM and Motorola for two) tend to take general purpose microprocessors and then strip them down to produce embedded offerings, Nat Semi is working from scratch - it says its core sizes will be significantly smaller than other RISC cores, will require less power and will eliminate the complexity attendant with general purpose RISC.
On the code-size reduction front, NSC has taken the unusual step of allowing variable length instructions in a RISC architecture - the result, it says, is that the 32bit implementation of Piranha has code densities similar to Motorola's 68K while the 16bit version produces even tighter code. Variable length instructions do not sound particularly RISCy, but NSC says that they are designed with a format that makes them easy for the chip to decode and despatch.
As for the size of the silicon; NSC certainly seems to have delivered. Pirahna 16, built in 0.8 micron silicon, has a core size of just 3 square mm. The 32bit implementation is 4.5 square mm. That is even smaller that the ARM-7 core. Because of the core's simplicity, performance is not blazing - better that ARM-6 and an Intel 386 at 25MHz, but worse than the ARM-7. At 30MHz the 32-bit part manages 43k Drhystones/second; the 16-bit version can do 33k Drhystones/second. However, NSC does claim performance leadership in the rather curious measure of 'performance per mm". When will it appear? The company is saying that product announcements will follow next year.