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Section Two: Forgotten/Innovative Designs before the Great Dark Cloud

Part I: RCA 1802, weirdness at its best (1974) .

The RCA 1802 was an odd beast, extremely simple and fabricated in CMOS, which allowed it to run at 6.4 MHz or suspended with the clock stopped (very fast for 1974, but needing 10V, and with a bit-serial ALU to limit complexity). It was a single chip version of the previous two-chip 1801, an 8 bit processor, with 16 bit addressing, but the major features were its extreme simplicity, and the flexibility of its large register set. Simplicity was the primary design goal, and in that sense it was one of the first "RISC" chips.

It had sixteen 16-bit registers, which could be accessed as thirty-two 8 bit registers, and an accumulator D used for arithmetic and memory access - memory to D, then D to registers, and vice versa, using one 16-bit register as an address. This led to one person describing the 1802 as having 32 bytes of RAM and 65535 I/O ports. It also had early DMA support. A 4-bit control register P selected any one general register as the program counter, while control registers X and N selected registers for I/O Index, and the operand for current instruction. All instructions were 8 bits - a 4-bit op code (total of 16 operations) and 4-bit operand register stored in N.

Register R0 pointed to the address used by the DMA circutry. R1 pointed to the interrupt service routine. There was no status register, but a number of flags available corresponded to carry bit, four pin inputs and one output, and interrupt enable.

There was no real conditional branching (there were conditional skips which could implement it, though), no subroutine support, and no actual stack, but clever use of the register set allowed these to be implemented - for example, R2 was usually used for a stack pointer, and changing P to another register allowed jump to a subroutine. Similarly, on an interrupt P and X were saved (to register T), then R1 and R2 were selected for P and X until an RTI restored them.

A later version, the 1804, was enhanced, adding several Forth language primitives (Forth is commonly used in control applications), and on-chip ROM and RAM (the 1805 and 1806 variants omit ROM or RAM).

Apart from the COSMAC microcomputer kit, the 1802 saw action in some video games from RCA and Radio Shack, and the chip is the heart of the Voyager, Viking and Galileo (along with some AMD 2900 bit slice processors) probes. One reason for this is that a version of the 1802 used silicon on sapphire (SOS) technology, which leads to radiation and static resistance, ideal for space operation. Was still available from Harris Semiconductors before finally being discontinued. It's low power consumption made it ideal for other remote systems, such as in Plessey Payphones (UK) which were powered entirely through the phone line or from solar panels.

The "RCA RP-1802" name was later applied to a budget-priced cassette player.

Embedded Processor and Microcontroller primer and FAQ:
COSMAC ELF and the TinyELF Emulator - The 1802 in Microcomputer History:
Lowell O. Turner's Home Page - 1802

Part II: Fairchild F8, Register windows .

The F8 was an 8 bit processor. The processor itself didn't have an address bus - program and data memory access were contained in separate units, which reduced the number of pins, and the associated cost (though single-chip versions became available). It featured one 8-bit accumulator, and 64 "scratchpad" registers, accessed by the ISAR register in cells (windows) of eight, which meant external RAM wasn't always needed for small applications. In addition, the 2-chip processor didn't need support chips, unlike others which needed seven or more. The F8 inspired other similar CPUs, such as the Intel 8048.

The use of the ISAR register allowed a subroutine to be entered without saving a bunch of registers, speeding execution - the ISAR would just be changed. Special purpose registers were stored in the second cell (regs 9-15), and the first eight registers were accessed directly (globally). The idea was to support structured (subroutine-oriented, without gotos) programming - JUMP instructions overwrote the accumulator.

The windowing concept was useful, but only the register pointed to by the ISAR could be accessed - to access other registers the ISAR was incremented or decremented through the window.

The second chip provides the 16-bit program counter, data counter, data counter buffer (can be swapped with data counter only - like a one-element stack), and stack pointer (for subroutines only). Mostek produced a single-chip version called the 3870 (pre-1978).

Fairchild ended up as part of National Semiconductor, before being spun off again in 1997.

Fairchild Semiconductor:

Part III: SC/MP, early advanced multiprocessing (April 1976) . . . .

The National Semiconductor SC/MP (Single Chip/Micro Processor (sometimes "Small Costeffective Micro Processor), nicknamed "Scamp") was a typical 8 bit processor intended for control applications (a simple BASIC 2.5K ROM was added to one version). It featured 16 bit addressing, with 12 address lines and the 4 upper lines borrowed from the data bus (it was common to borrow lines (sometimes all of them) from the data bus for addressing - however only the lower 12 index register/PC bits were incremented (4K pages), special instructions modified upper 4 bits). Internally, it included four index registers (P1 to P3, plus the PC/P0) and two 8 bit registers. It had no stack pointer or subroutine instructions (though they could be emulated with index registers). During interrupts, the PC and P3 were swapped. It was meant for embedded control, and many features were omitted for cost reasons. It was also bit serial internally to keep it cheap.

The unique feature was the ability to completely share a system bus with other processors. Most processors of the time assumed they were the only ones accessing memory or I/O devices. Multiple SC/MPs (as well as other intelligent devices, such as DMA controllers) could be hooked up to the bus. A control line (ENOUT (Enable Out) to ENIN) could be chained along the processors to allow cooperative processing. This was very advanced for the time, compared to other CPUs, but the bit-serial CPU was slow (even simple instruction took 5-7 cycles, while memory access was 2 cycles, which allowed them to share a memory bus without saturating it (up to three), as opposed to a 6502 which could share memory with at most one other CPU, and only then because of the way the CPU clock was used). However this feature was almost never used for multiprocessing.

In addition to I/O ports like the 8080, the SC/MP also had instructions and one pin for serial input and one for output.

National semiconductor also produced the IMP series (originally cards, later microprocessors in 4, 8, 12, and 16 bit versions) and 16-bit PACE. The SC/MP was eventually replaced with the COP4 (4 bit) and COP8 (8 bit) embedded controllers, with only two index registers, but adding stack support.

National Semiconductor:
National Semiconductor Microcontroller Technology:
SC/MP Elektor emulator:

Part IV: F100-L, a self expanding design .

The Ferranti F100-L was designed by a British company for the British Military. It was a 16-bit processor (the ALU was a slow bit-serial design) with limited 8-bit support, and 16-bit addressing, but it could only access 32K of memory (1 bit for indirection).

The unique feature of the F100-L was that it had a complete control bus available for a coprocessor that could be added on. Any instruction the F100-L couldn't decode was sent directly to the coprocessor for processing. Applications for coprocessors at the time were limited, but the design is still used in some modern processors, such as the National Semiconductor 320xx series, which included FPU, MMU, and other coprocessors that could just be added to the CPU's coprocessor bus in a chain. Other units not foreseen could be added later.

Ferranti, which built the Ferranti Mark 1 (Britain's first commercial electronic computer), no longer makes microprocessors.

National Semiconductor:
My History With Computers:

Part V: The Western Digital 3-chip CPU (June 1976) .

The Western Digital MCP-1600 was probably the most flexible processor available. It consisted of at least four separate chips, including the control circuitry unit, the ALU, two or four ROM chips with customisable microcode (like the old 4-bit Texas Instruments TMS 1000), and timing circuitry. It doesn't really count as a microprocessor, but neither do bit-slice processors (AMD 2901).

The ALU chip contained twenty six 8 bit registers and an 8 bit ALU, while the control unit supervised the moving of data, memory access, and other control functions. The ROM allowed the chip to function as either an 8 bit chip or 16 bit, with clever use of the 8 bit ALU. Even more, microcode allowed the addition of floating point routines (40 + 8 bit format), simplifying programming (and possibly producing a Floating Point Coprocessor).

Two standard microcode ROMS were available. This flexibility was one reason it was also used to implement the DEC LSI-11 processor as well as the WD Pascal Microengine.

Part VI: Intersil 6100, old design in a new package . . .

The IMS 6100 was a single chip design of the PDP-8 minicomputer (1965) from DEC (low cost successor to the PDP-5 (1963)). The old PDP-8 design was very strange, and if it hadn't been so popular, an awkward CPU like the 6100 would have never had a reason to exist.

The 6100 was a 12 bit processor, which had exactly three registers - the PC, AC (an accumulator), and MQ. All 2 operand instructions read AC and MQ, and wrote back to AC. It had a 12 bit address bus, limiting RAM to only 4K. Memory references were 7 bit (128 word) offset either from address 0, or the PC.

It had no stack. Subroutines stored the PC in the first word of the subroutine code itself, so recursion wasn't possible without fancy programming.

4K RAM was pretty much hopeless for general purpose use. The 6102 support chip (included on chip in the 6120) added 3 address lines, expanding memory to 32K the same way that the PDP-8/E expanded the PDP-8. Two registers, IFR and DFR, held the page for instructions and data respectively (IFR always used until a data address was detected). At the top of the 4K page, the PC wrapped back to 0, so the last instruction on a page had to load a new value into the IFR if execution was to continue.

The PDP-8 itself was succeeded by the PDP-11 (though a version called the PDP-12 was produced, it was part of the PDP-8 series, not a replacement). The IMS 6120 was used in the DECmate (1980), DEC's original competition for the IBM PC, but lacked the processor and RAM capacity (a Z-80 or 8086 card could be added (reducing the 6120 to an I/O coprocessor) but lacked IBM PC compatability). DEC also tried competing with the 8086 based Rainbow, and the PDP-11 based PRO-325 personal computers, but none caught on.

Intersil was eventually bought by Harris Semiconductors, which produces versions of the 8088 and 8086, 1802, and 68HC05.

PDP-8 Models and Options:
Harris Semiconductors:

Part VII: NOVA, another popular adaptation . . . .

Like the PDP-8, the Data General Nova was also copied, not just in one, but two implementations - the Data General MN601 (MicroNova), and Fairchild 9440. However, the NOVA (1969) was a more mature design (by PDP-8 designer Edson DeCastro, who founded Data General from DEC after an internal competition for the PDP-8 replacement chose Gordon Bell's new design which became the PDP-11, rather than DeCastro's extended PDP-8 design).

The NOVA had four 16-bit accumulators, AC0 to AC3. There were also 15-bit system registers - Program Counter, Stack pointer, and Stack Frame pointer (the last two were only on the Nova 3, MicroNova (singel-chip Nova 3), and Nova 4, not the original Nova CPU). AC2 and AC3 could be used for indexed addresses. The Fairchild CPU added a single level indirection bit, allowing 16 bit addresses. Apart from the small register set, the NOVA was an ordinary CPU design.

Another CPU, the National Semiconductor PACE, was based on the NOVA design, but featured 16 bit addressing, more addressing modes, and a 10 level stack (like the 8008), but lacked hardware multiply and divide.

The 16/32 bit ECLIPSE (1973) was Data General's higher end complement to the 16 bit Nova, adding 16 and 32-bit instructions. Like the Nova, the ECLIPSE had four 16 bit integer accumulators, added four stack registers. There are also twelve special purpose registers. Registers were expanded to 32-bits, four 64 bit floating point registers, virtual memory, and complex instructions (including a set to skip next instruction based on operation results, a primitive type of predicated instructions) were added in the MV series (1978/79) (Originally MV/Eclipse, renamed MV/8000). The ECLIPSE was eventually implemented in a microprocessor form as well.

Data General later switched architectures and became an early supporter of the Motorola 88K series load-store microprocessor in the AViiON Unix based systems (rumour had it that designers originally wanted to call it the Nova II, but that idea was rejected, so instead they reversed the name and inserted the II in the middle, switching upper and lower case. In reality, there had already been Novas up to 4, so II (meaning 2) would have been a step backward. The name "Avion" was simply chosen, and the marketing department "enhanced" it - possibly someone there picked up on the Nova/Avion near-palindrome). Rumour was that MIPS CPUs were preferred by designers, but "bad blood" between ex-DG MIPS president and current DG management overrode that decision. Unfortunately, Motorola didn't keep up with competing CPUs (eventually switching its main support to the PowerPC), forcing Data General to invest heavily in multiprocessing to boost performance, until the company gave up on Motorola and switched to Intel Pentium CPUs (as Intergraph did). It then switched to storage systems (CLARiiON), and was bought by storage products company EMC.

This has nothing to actually do with the Nova CPU, but is a little bit interesting anyway.

Data General:
Data General Nova:

Part VIII: Signetics 2650, enhanced accumulator based (1978?) .

Superficially similar to the PDP-8 (and IMS 6100), the Signetics 2650 was based around a set of 8 bit registers with R0 used as an accumulator, and six other registers arranged in two sets (R1A-R3A and R1B-R3B) - a status bit determined which register bank was active. The other registers were generally used for address calculations (ex. offsets) within the 15 bit address range. This kept the instruction set simple - all loads/stores to registers went through R0.

It also had a subroutine stack of eight 15 bit elements, with no provision for spilling over into memory.

Signetics was bought by Valvo, which was later bought by Phillips.

Part IX: Signetics 8x300, Early cambrian DSP ancestor (1978) . .

Originally developed by a company called SMS, the 8x300 was bought and became a product of Signetics. Presented as a microcontroller, it had many DSP-like features (plus a bipolar fabrication) that made if very fast at the time, for some applications at least, but lacked many standard features and was slighly out of step with some conventions of the time (for example, bits were numbered in reverse, bit 0 as MSB and 7 as LSB).

The 8x300 could address sixteen registers, but some register addresses were used to specify non-register operations, so only eight 8-bit general purpose registers were available - R0 (AUX, the auxiliary register), R1 to R6, and R9 (R11 octal in assembler notation). Register R8 (OVF) was a single carry bit. In addition, an 8-bit I/O buffer register IVB was available, and is the only way to access data memory (similar to the D register in the RCA 1802) - all data was through 8-bit I/O ports, organised as two banks (left and right) of 256 each plus an address indicating which port of that bank I/O operations would use. The exact operation is specified by the source or destination register field - if it's not an actual register, then it signifies an operation. Ports could be attached directly to memory, or two ports could be used to generate an address, with another as a data buffer if more storage was needed.

The CPU consisted of multiple units strung together in a pipeline (one 16-bit instruction at a time, no overlapping stages as in modern CPUs). The first operand could be taken from the IVB (as an I/O operation from an I/O port in the left or right bank) or any of the general registers, the second operand (if any) came from the AUX register. The first operand would be processed through a rotate unit, then a mask unit, to the ALU which performed ony four operations - MOV, ADD, AND and XOR. The result would be returned either to a general register, or could would be processed through a shifter and merge unit to the IVB register (and output to the appropriate left or right I/O port) - this would allow a subfield of the IVB to be replaced by bits from the result, instead of the whole register.

The design was also limited with no interrupt support, no stack or index registers (though the port addresses could function as such), and no subroutine support (the XEC instruction would execute an instruction without incremeting the PC, and could be used to implement subroutines). Data values couldn't be accessed from program memory.

A Second Interview with John Fletcher:
Old Stories about Old Computers:

Part X: Hitachi 6301 - Small and microcoded (1983) .

The HD6301 was an 8-bit CPU designed using microcode to bring the simpler design techniques of 16 and 32 bit CPUs at the time down to 8-bit designs. Inspired by the Motorola 6800, the 6301 featured A and B accumulators, one stack and one index register. These, along with the PC, were mapped to a bank of sixteen 8-bit registers (R0L, R0H, R1L etc. up to R7H), which along with two data buffer registers (DBR and DBL), and memory address registers (MARL and MARH), were accessed by the microcode to execute the CPU instructions using one 8-bit ALU and a simpler 8-bit arithmatic unit. A simple 2-stage pipeline was used.

Part XI: Motorola MC14500B ICU, one bit at a time .

Probably the limit in small processors was the 1 bit 14500B from Motorola. It had a 4 bit instruction, and controlled a single data read/write line, used for application control. It had no address bus - that was an external unit that was added on. Another CPU could be used to feed control instructions to the 14500B in an application.

It had only 16 pins, less than a typical RAM chip, and ran at 1 MHz.

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