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PA-RISC Identification
PA7xxx-PA8xxx
Updated 02-10-2006

Model Package Introduced Width Frequency Process Transistors L1 Cache L2 Cache Units Notes
PCX-S
PA-7000
271 PGA 1989 32 66 1u 0.58M 512K* - 1 INT T1
T2
T3
T4
PCX-T
PA-7100
504 SPGA 1992 32 33-125 0.8u 0.85M 3MB* - 1 INT
1 FP
9247 = 2.3
9326 = 2.6
9341 = 3.3
PCX-L
PA-7100L
C

431 SPGA 1992 32 60-100 0.75u 0.90M 1K 2MB* 2 INT
1 FP
9339 = 2.1
9439 = 2.3
9525 = 2.4
PCX-T
PA-7150
431 SPGA 1994 32 125 0.8u 0.85M 3MB* - 1 INT
1 FP
 
PCX-T
PA-7150LC
431 SPGA 1994 32 125 0.8u 0.85M 3MB* - 1 INT
1 FP
9605 = 2.0
PCX-T'
PA-7200
539 SPGA 1994 32 140 0.55u 1.26M 2K 3MB* 2 INT
1 FP
9528 = 3.1
9542 = 3.2
PCX-L2
PA-7300LC
463 SPGA 1996 32 133-180 0.5u 9.2M 128K 8MB* 2 INT
1 FP
9642 = 2.0
9716 = 4.0
64-Bit PA-RISC Implementations
PCX-U
PA-8000
1085 LGA 1996 64 160-230 0.5u 3.8M 2M* -

4 INT
4 FP
2 L/S

9639 = 2.5
9710 = 3.1
PCX-U+
PA-8200
1085 LGA 1997 64 200-300 0.5u 3.8M 4M* - 4 INT
4 FP
2 L/S
 
PCX-W
PA-8500
544 LGA 1998 64 360-440 0.25u 140M 1.5M - 4 INT
4 FP
2 L/S
 
PCX-W+
PA-8600
544 LGA 2000 64 552 0.25u 140M 1.5M - 4 INT
4 FP
2 L/S
 
PCX-W2
PA-8700
544 LGA 2001 64 800-875 0.18u 186M 2.25M - 4 INT
4 FP
2 L/S
 
Mako
PA-8800
544 LGA 2003 64 900-1000 0.13u 300M 1.5M/core 32MB 8 INT
8 FP
4 L/S
Dual core 8700
PA-8900   2005 64 1000-1100 0.13u   1.5M/core 64MB    
NON HP PA-RISC CPUs
Hitachi
PA/50
160 PQFP 1993 32 60 0.6u 1.28M 12K - 1 INT
1 FP
 
Hitachi
HARP-1
    32 150 0.6u 2.8M 24K 1M* 1 INT
1 FP
 
  NOTES:
LC
*
T1
T2
T3
T4

No mounting screw threads
Off Die Cache
Rectangle plate, 36 caps, 2 mounts
Square plate, 36 caps, 1 mount
Rectangle plate, 15 caps, 2 mounts
Round heatspreader, 15 caps, no mount

PA-7000 (PCX-S)

Overview

This really was a multichip CPU and was used in Nova severs. It is the first ose of PA 1.1

Details

PA-RISC Version 1.1a (32 bit)
FPU External
Process 1.0u 2-Layer CMOS
Die Size 14.2 x 14.2 mm2 die
Introduced 1987?
   
   

PA-7100/PA-7150 (PCX-T) (Thunderbird)


PA-7100

Overview

The 7100 is a true superscalar CPU, with ALU units as well as an onboard FPU.
The 7150 is an enhanced 7100 with a higher clock speed.

Details

PA-RISC Version 1.1b (32 bit)
FPU Single FPU
Process 0.8u 3-Layer CMOS
Die Size 14.0 x 14.0 mm2 die
Introduced 1992
   
   

PA-7100LC (PCX-L) (Hummingbird)

PA-7100LC

Overview

This is a low cost CPU meant to integrate many of the support chips (FPU MPU etc) on the same chip

Details

PA-RISC Version 1.1c (32 bit)
FPU Single FPU
Process 0.75u 3-Layer CMOS
Die Size 14.2 x 14.2 mm2 die
Introduced 1994
   
   

PA-7200 (PCX-T') (Thunderbird')

Overview

The PA-7200 is a die shrunk and frequency enhanced PA-7100, with a few extra enhancements to bring it to PA 1.1d revision level. It still requires off chip cache running at core speed. (140MHz)

Details

PA-RISC Version 1.1d (32 bit)
FPU Single FPU
Process 0.55u 3-Layer CMOS
Die Size 14.0 x 15.0 mm2 die
Introduced 1995
   
   

PA-7300LC (PCX-L2) (Velociraptor)

PA-7300LCPA-7300LC

Overview

The PA-7300LC is an enhanced 7100LC with ondie L1 cache (courtesy of the process shrink)

Details

PA-RISC Version 1.1e (32 bit)
FPU Single FPU
Process 0.50u 4-Layer CMOS
Die Size 15.3 x 17.0 mm2 die
Introduced 1996
   
   

PA-8000 (PCX-U) (Onyx)

PA-8000PA-8000

Overview

The PA-8000 is the first chip to implement the 64-bit PA-RISC 2.0 architecture. It again, in HP tradition, has large off de primary caches.

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.50u 5-Layer CMOS
Die Size 17.7 x 19.6 mm2 die
Introduced 1996
   
   

PA-8200 (PCX-U+) (Vulcan)

Overview

Nothing more then a PA-8000 with a few sdesign fixes implemented.

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.50u 5-Layer CMOS
Die Size 17.7 x 19.6 mm2 die
Introduced 1997
   
   

PA-8500 (PCX-W) (Vulcan)

PA-8500PA-8500

Overview

The PA-8500 is a direct decendent of the 8000. It features a higher clock speed and a MASSIVE 1.5MB on die L1 cache (most other chips of the time were running 32kB L1 caches)

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.25u 5-Layer CMOS
Die Size 21.3 x 22.0 mm2 die
Introduced 1998
   
   

PA-8600 (PCX-W+) (Landshark)

PA-8600PA-8600

Overview

A slightly enhanced PA-8500 made to work on a new fab process. Very few changes to the deisgn itself.

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.25u 5-Layer CMOS
Die Size 21.3 x 22.0 mm2 die
Introduced 2000
   
   

PA-8700 (PCX-W2) (Piranha)

Overview

The PA-8700 is again a enhanced and clock speed increased 8500 The PA-8700 was manufactured by IBM, in contrast to the PA-8500 and PA-8600, which were fabbed by Intel, since HP stopped upgrading its fabs long ago. HP still makaes custom chips in its old fabs)

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.18u 7-Layer CMOS SOI
Die Size 16.0 x 19.0 mm2 die
Introduced 2001
   
   

PA-8800 (PCX-??) (Mako)

Overview

The PA-8800, codenamed Mako, features 2 independent microprocessors on a single die. Thus each "chip" forms a 2-way SMP set. Each processor on the 8800 has a 1.5 MB L1 cache, but HP is leaving behind its L1-only design custom by including 32 MB of L2 cache using separate chips. The Runway bus has been replaced by the 6.4 GB/s Itanium2 bus, allowing greater bandwidth and the use of otherwise very similar server designs for both PA-RISC and Itanium.

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.13u 7-Layer CMOS SOI Copper
Die Size ??
Introduced 2003
   
   

PA-8900 (PCX-??)

 

Overview

The PA-8900 is similar to the 8800, but features a faster 64 MB shared L2 and slight core improvements such as better error detection and correction on caches. The cahce has also been brought closer to the cores, which helps reduce latenecy. It is not a die shrink of the 8800, as was earlier rumored. It is the last in the PA-RISC line. THe PA-8900 will be the last PA-RISC CPU and is used in the HP 9000 server line.

Details

PA-RISC Version 2.0 (64 bit)
FPU Quadruple FPU's
Process 0.13u 7-Layer CMOS SOI
Die Size ??
Introduced 2005
   
   

Hitachi PA/50

Overview

The PA/50 were PA-RISC version 1.1 compatible PA-RISC CPUs designed and manufactured by Hitachi. Two designs were developed: the ' M' and ' L'. The ' L' being a lower cost lowe voltage (3.3V) embedded version.. They were meant as personal workstation or high-end embedded controllers. Hitachi also integrates L1 cache onto the die

Details

PA-RISC Version 1.1 (32 bit)
FPU SIngle Pipelined FPU
Process 0.6u 3-Layer CMOS
Die Size 11.5 x 12.0 mm2 die
Introduced 1993
   
   

Hitachi HARP-1

Overview

The HARP-1 also was a PA-RISC version 1.1 compatible CPU from Hitachi; It was a enhanced PA/50L and also ran at 3.3V

Details

PA-RISC Version 1.1 (32 bit)
FPU SIngle Pipelined FPU
Process 0.6u 3+1-Layer CMOS (Al + Tungsten)
Die Size 16.2 x 16.5 mm2 die
Introduced 1994
   
   

Sources:
HP Datasheets
Open-PA.Net <- A great PA-RISC resource


 

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